1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos4412 SoC device tree source 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 9 * based board files can include this file and provide values for board specfic 10 * bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional 14 * nodes can be added to this file. 15 */ 16 17#include "exynos4.dtsi" 18 19#include "exynos4-cpu-thermal.dtsi" 20 21/ { 22 compatible = "samsung,exynos4412", "samsung,exynos4"; 23 24 aliases { 25 pinctrl0 = &pinctrl_0; 26 pinctrl1 = &pinctrl_1; 27 pinctrl2 = &pinctrl_2; 28 pinctrl3 = &pinctrl_3; 29 fimc-lite0 = &fimc_lite_0; 30 fimc-lite1 = &fimc_lite_1; 31 mshc0 = &mshc_0; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu-map { 39 cluster0 { 40 core0 { 41 cpu = <&cpu0>; 42 }; 43 core1 { 44 cpu = <&cpu1>; 45 }; 46 core2 { 47 cpu = <&cpu2>; 48 }; 49 core3 { 50 cpu = <&cpu3>; 51 }; 52 }; 53 }; 54 55 cpu0: cpu@a00 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a9"; 58 reg = <0xA00>; 59 clocks = <&clock CLK_ARM_CLK>; 60 clock-names = "cpu"; 61 operating-points-v2 = <&cpu0_opp_table>; 62 #cooling-cells = <2>; /* min followed by max */ 63 }; 64 65 cpu1: cpu@a01 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a9"; 68 reg = <0xA01>; 69 clocks = <&clock CLK_ARM_CLK>; 70 clock-names = "cpu"; 71 operating-points-v2 = <&cpu0_opp_table>; 72 #cooling-cells = <2>; /* min followed by max */ 73 }; 74 75 cpu2: cpu@a02 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a9"; 78 reg = <0xA02>; 79 clocks = <&clock CLK_ARM_CLK>; 80 clock-names = "cpu"; 81 operating-points-v2 = <&cpu0_opp_table>; 82 #cooling-cells = <2>; /* min followed by max */ 83 }; 84 85 cpu3: cpu@a03 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a9"; 88 reg = <0xA03>; 89 clocks = <&clock CLK_ARM_CLK>; 90 clock-names = "cpu"; 91 operating-points-v2 = <&cpu0_opp_table>; 92 #cooling-cells = <2>; /* min followed by max */ 93 }; 94 }; 95 96 cpu0_opp_table: opp-table0 { 97 compatible = "operating-points-v2"; 98 opp-shared; 99 100 opp-200000000 { 101 opp-hz = /bits/ 64 <200000000>; 102 opp-microvolt = <900000>; 103 clock-latency-ns = <200000>; 104 }; 105 opp-300000000 { 106 opp-hz = /bits/ 64 <300000000>; 107 opp-microvolt = <900000>; 108 clock-latency-ns = <200000>; 109 }; 110 opp-400000000 { 111 opp-hz = /bits/ 64 <400000000>; 112 opp-microvolt = <925000>; 113 clock-latency-ns = <200000>; 114 }; 115 opp-500000000 { 116 opp-hz = /bits/ 64 <500000000>; 117 opp-microvolt = <950000>; 118 clock-latency-ns = <200000>; 119 }; 120 opp-600000000 { 121 opp-hz = /bits/ 64 <600000000>; 122 opp-microvolt = <975000>; 123 clock-latency-ns = <200000>; 124 }; 125 opp-700000000 { 126 opp-hz = /bits/ 64 <700000000>; 127 opp-microvolt = <987500>; 128 clock-latency-ns = <200000>; 129 }; 130 opp-800000000 { 131 opp-hz = /bits/ 64 <800000000>; 132 opp-microvolt = <1000000>; 133 clock-latency-ns = <200000>; 134 opp-suspend; 135 }; 136 opp-900000000 { 137 opp-hz = /bits/ 64 <900000000>; 138 opp-microvolt = <1037500>; 139 clock-latency-ns = <200000>; 140 }; 141 opp-1000000000 { 142 opp-hz = /bits/ 64 <1000000000>; 143 opp-microvolt = <1087500>; 144 clock-latency-ns = <200000>; 145 }; 146 opp-1100000000 { 147 opp-hz = /bits/ 64 <1100000000>; 148 opp-microvolt = <1137500>; 149 clock-latency-ns = <200000>; 150 }; 151 opp-1200000000 { 152 opp-hz = /bits/ 64 <1200000000>; 153 opp-microvolt = <1187500>; 154 clock-latency-ns = <200000>; 155 }; 156 opp-1300000000 { 157 opp-hz = /bits/ 64 <1300000000>; 158 opp-microvolt = <1250000>; 159 clock-latency-ns = <200000>; 160 }; 161 opp-1400000000 { 162 opp-hz = /bits/ 64 <1400000000>; 163 opp-microvolt = <1287500>; 164 clock-latency-ns = <200000>; 165 }; 166 cpu0_opp_1500: opp-1500000000 { 167 opp-hz = /bits/ 64 <1500000000>; 168 opp-microvolt = <1350000>; 169 clock-latency-ns = <200000>; 170 turbo-mode; 171 }; 172 }; 173 174 175 soc: soc { 176 177 pinctrl_0: pinctrl@11400000 { 178 compatible = "samsung,exynos4x12-pinctrl"; 179 reg = <0x11400000 0x1000>; 180 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 181 }; 182 183 pinctrl_1: pinctrl@11000000 { 184 compatible = "samsung,exynos4x12-pinctrl"; 185 reg = <0x11000000 0x1000>; 186 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 187 188 wakup_eint: wakeup-interrupt-controller { 189 compatible = "samsung,exynos4210-wakeup-eint"; 190 interrupt-parent = <&gic>; 191 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 192 }; 193 }; 194 195 pinctrl_2: pinctrl@3860000 { 196 compatible = "samsung,exynos4x12-pinctrl"; 197 reg = <0x03860000 0x1000>; 198 interrupt-parent = <&combiner>; 199 interrupts = <10 0>; 200 }; 201 202 pinctrl_3: pinctrl@106e0000 { 203 compatible = "samsung,exynos4x12-pinctrl"; 204 reg = <0x106E0000 0x1000>; 205 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 206 }; 207 208 sram@2020000 { 209 compatible = "mmio-sram"; 210 reg = <0x02020000 0x40000>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 ranges = <0 0x02020000 0x40000>; 214 215 smp-sram@0 { 216 compatible = "samsung,exynos4210-sysram"; 217 reg = <0x0 0x1000>; 218 }; 219 220 smp-sram@2f000 { 221 compatible = "samsung,exynos4210-sysram-ns"; 222 reg = <0x2f000 0x1000>; 223 }; 224 }; 225 226 pd_isp: power-domain@10023ca0 { 227 compatible = "samsung,exynos4210-pd"; 228 reg = <0x10023CA0 0x20>; 229 #power-domain-cells = <0>; 230 label = "ISP"; 231 }; 232 233 l2c: cache-controller@10502000 { 234 compatible = "arm,pl310-cache"; 235 reg = <0x10502000 0x1000>; 236 cache-unified; 237 cache-level = <2>; 238 prefetch-data = <1>; 239 prefetch-instr = <1>; 240 arm,tag-latency = <2 2 1>; 241 arm,data-latency = <3 2 1>; 242 arm,double-linefill = <1>; 243 arm,double-linefill-incr = <0>; 244 arm,double-linefill-wrap = <1>; 245 arm,prefetch-drop = <1>; 246 arm,prefetch-offset = <7>; 247 }; 248 249 clock: clock-controller@10030000 { 250 compatible = "samsung,exynos4412-clock"; 251 reg = <0x10030000 0x18000>; 252 #clock-cells = <1>; 253 }; 254 255 isp_clock: clock-controller@10048000 { 256 compatible = "samsung,exynos4412-isp-clock"; 257 reg = <0x10048000 0x1000>; 258 #clock-cells = <1>; 259 power-domains = <&pd_isp>; 260 clocks = <&clock CLK_ACLK200>, 261 <&clock CLK_ACLK400_MCUISP>; 262 clock-names = "aclk200", "aclk400_mcuisp"; 263 }; 264 265 timer@10050000 { 266 compatible = "samsung,exynos4412-mct"; 267 reg = <0x10050000 0x800>; 268 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 269 clock-names = "fin_pll", "mct"; 270 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 271 <&combiner 12 5>, 272 <&combiner 12 6>, 273 <&combiner 12 7>, 274 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; 275 }; 276 277 watchdog: watchdog@10060000 { 278 compatible = "samsung,exynos5250-wdt"; 279 reg = <0x10060000 0x100>; 280 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clock CLK_WDT>; 282 clock-names = "watchdog"; 283 samsung,syscon-phandle = <&pmu_system_controller>; 284 }; 285 286 adc: adc@126c0000 { 287 compatible = "samsung,exynos4212-adc"; 288 reg = <0x126C0000 0x100>; 289 interrupt-parent = <&combiner>; 290 interrupts = <10 3>; 291 clocks = <&clock CLK_TSADC>; 292 clock-names = "adc"; 293 #io-channel-cells = <1>; 294 samsung,syscon-phandle = <&pmu_system_controller>; 295 status = "disabled"; 296 }; 297 298 g2d: g2d@10800000 { 299 compatible = "samsung,exynos4212-g2d"; 300 reg = <0x10800000 0x1000>; 301 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 303 clock-names = "sclk_fimg2d", "fimg2d"; 304 iommus = <&sysmmu_g2d>; 305 }; 306 307 mshc_0: mmc@12550000 { 308 compatible = "samsung,exynos4412-dw-mshc"; 309 reg = <0x12550000 0x1000>; 310 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 fifo-depth = <0x80>; 314 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; 315 clock-names = "biu", "ciu"; 316 status = "disabled"; 317 }; 318 319 sysmmu_g2d: sysmmu@10a40000 { 320 compatible = "samsung,exynos-sysmmu"; 321 reg = <0x10A40000 0x1000>; 322 interrupt-parent = <&combiner>; 323 interrupts = <4 7>; 324 clock-names = "sysmmu", "master"; 325 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 326 #iommu-cells = <0>; 327 }; 328 329 sysmmu_fimc_isp: sysmmu@12260000 { 330 compatible = "samsung,exynos-sysmmu"; 331 reg = <0x12260000 0x1000>; 332 interrupt-parent = <&combiner>; 333 interrupts = <16 2>; 334 power-domains = <&pd_isp>; 335 clock-names = "sysmmu"; 336 clocks = <&isp_clock CLK_ISP_SMMU_ISP>; 337 #iommu-cells = <0>; 338 }; 339 340 sysmmu_fimc_drc: sysmmu@12270000 { 341 compatible = "samsung,exynos-sysmmu"; 342 reg = <0x12270000 0x1000>; 343 interrupt-parent = <&combiner>; 344 interrupts = <16 3>; 345 power-domains = <&pd_isp>; 346 clock-names = "sysmmu"; 347 clocks = <&isp_clock CLK_ISP_SMMU_DRC>; 348 #iommu-cells = <0>; 349 }; 350 351 sysmmu_fimc_fd: sysmmu@122a0000 { 352 compatible = "samsung,exynos-sysmmu"; 353 reg = <0x122A0000 0x1000>; 354 interrupt-parent = <&combiner>; 355 interrupts = <16 4>; 356 power-domains = <&pd_isp>; 357 clock-names = "sysmmu"; 358 clocks = <&isp_clock CLK_ISP_SMMU_FD>; 359 #iommu-cells = <0>; 360 }; 361 362 sysmmu_fimc_mcuctl: sysmmu@122b0000 { 363 compatible = "samsung,exynos-sysmmu"; 364 reg = <0x122B0000 0x1000>; 365 interrupt-parent = <&combiner>; 366 interrupts = <16 5>; 367 power-domains = <&pd_isp>; 368 clock-names = "sysmmu"; 369 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; 370 #iommu-cells = <0>; 371 }; 372 373 sysmmu_fimc_lite0: sysmmu@123b0000 { 374 compatible = "samsung,exynos-sysmmu"; 375 reg = <0x123B0000 0x1000>; 376 interrupt-parent = <&combiner>; 377 interrupts = <16 0>; 378 power-domains = <&pd_isp>; 379 clock-names = "sysmmu", "master"; 380 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, 381 <&isp_clock CLK_ISP_FIMC_LITE0>; 382 #iommu-cells = <0>; 383 }; 384 385 sysmmu_fimc_lite1: sysmmu@123c0000 { 386 compatible = "samsung,exynos-sysmmu"; 387 reg = <0x123C0000 0x1000>; 388 interrupt-parent = <&combiner>; 389 interrupts = <16 1>; 390 power-domains = <&pd_isp>; 391 clock-names = "sysmmu", "master"; 392 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, 393 <&isp_clock CLK_ISP_FIMC_LITE1>; 394 #iommu-cells = <0>; 395 }; 396 397 bus_dmc: bus-dmc { 398 compatible = "samsung,exynos-bus"; 399 clocks = <&clock CLK_DIV_DMC>; 400 clock-names = "bus"; 401 operating-points-v2 = <&bus_dmc_opp_table>; 402 samsung,data-clock-ratio = <4>; 403 #interconnect-cells = <0>; 404 status = "disabled"; 405 }; 406 407 bus_acp: bus-acp { 408 compatible = "samsung,exynos-bus"; 409 clocks = <&clock CLK_DIV_ACP>; 410 clock-names = "bus"; 411 operating-points-v2 = <&bus_acp_opp_table>; 412 status = "disabled"; 413 }; 414 415 bus_c2c: bus-c2c { 416 compatible = "samsung,exynos-bus"; 417 clocks = <&clock CLK_DIV_C2C>; 418 clock-names = "bus"; 419 operating-points-v2 = <&bus_dmc_opp_table>; 420 status = "disabled"; 421 }; 422 423 bus_dmc_opp_table: opp-table1 { 424 compatible = "operating-points-v2"; 425 426 opp-100000000 { 427 opp-hz = /bits/ 64 <100000000>; 428 opp-microvolt = <900000>; 429 }; 430 opp-134000000 { 431 opp-hz = /bits/ 64 <134000000>; 432 opp-microvolt = <900000>; 433 }; 434 opp-160000000 { 435 opp-hz = /bits/ 64 <160000000>; 436 opp-microvolt = <900000>; 437 }; 438 opp-267000000 { 439 opp-hz = /bits/ 64 <267000000>; 440 opp-microvolt = <950000>; 441 }; 442 opp-400000000 { 443 opp-hz = /bits/ 64 <400000000>; 444 opp-microvolt = <1050000>; 445 opp-suspend; 446 }; 447 }; 448 449 bus_acp_opp_table: opp-table2 { 450 compatible = "operating-points-v2"; 451 452 opp-100000000 { 453 opp-hz = /bits/ 64 <100000000>; 454 }; 455 opp-134000000 { 456 opp-hz = /bits/ 64 <134000000>; 457 }; 458 opp-160000000 { 459 opp-hz = /bits/ 64 <160000000>; 460 }; 461 opp-267000000 { 462 opp-hz = /bits/ 64 <267000000>; 463 }; 464 }; 465 466 bus_leftbus: bus-leftbus { 467 compatible = "samsung,exynos-bus"; 468 clocks = <&clock CLK_DIV_GDL>; 469 clock-names = "bus"; 470 operating-points-v2 = <&bus_leftbus_opp_table>; 471 interconnects = <&bus_dmc>; 472 #interconnect-cells = <0>; 473 status = "disabled"; 474 }; 475 476 bus_rightbus: bus-rightbus { 477 compatible = "samsung,exynos-bus"; 478 clocks = <&clock CLK_DIV_GDR>; 479 clock-names = "bus"; 480 operating-points-v2 = <&bus_leftbus_opp_table>; 481 status = "disabled"; 482 }; 483 484 bus_display: bus-display { 485 compatible = "samsung,exynos-bus"; 486 clocks = <&clock CLK_ACLK160>; 487 clock-names = "bus"; 488 operating-points-v2 = <&bus_display_opp_table>; 489 interconnects = <&bus_leftbus &bus_dmc>; 490 #interconnect-cells = <0>; 491 status = "disabled"; 492 }; 493 494 bus_fsys: bus-fsys { 495 compatible = "samsung,exynos-bus"; 496 clocks = <&clock CLK_ACLK133>; 497 clock-names = "bus"; 498 operating-points-v2 = <&bus_fsys_opp_table>; 499 status = "disabled"; 500 }; 501 502 bus_peri: bus-peri { 503 compatible = "samsung,exynos-bus"; 504 clocks = <&clock CLK_ACLK100>; 505 clock-names = "bus"; 506 operating-points-v2 = <&bus_peri_opp_table>; 507 status = "disabled"; 508 }; 509 510 bus_mfc: bus-mfc { 511 compatible = "samsung,exynos-bus"; 512 clocks = <&clock CLK_SCLK_MFC>; 513 clock-names = "bus"; 514 operating-points-v2 = <&bus_leftbus_opp_table>; 515 status = "disabled"; 516 }; 517 518 bus_leftbus_opp_table: opp-table3 { 519 compatible = "operating-points-v2"; 520 521 opp-100000000 { 522 opp-hz = /bits/ 64 <100000000>; 523 opp-microvolt = <900000>; 524 }; 525 opp-134000000 { 526 opp-hz = /bits/ 64 <134000000>; 527 opp-microvolt = <925000>; 528 }; 529 opp-160000000 { 530 opp-hz = /bits/ 64 <160000000>; 531 opp-microvolt = <950000>; 532 }; 533 opp-200000000 { 534 opp-hz = /bits/ 64 <200000000>; 535 opp-microvolt = <1000000>; 536 opp-suspend; 537 }; 538 }; 539 540 bus_display_opp_table: opp-table4 { 541 compatible = "operating-points-v2"; 542 543 opp-160000000 { 544 opp-hz = /bits/ 64 <160000000>; 545 }; 546 opp-200000000 { 547 opp-hz = /bits/ 64 <200000000>; 548 }; 549 }; 550 551 bus_fsys_opp_table: opp-table5 { 552 compatible = "operating-points-v2"; 553 554 opp-100000000 { 555 opp-hz = /bits/ 64 <100000000>; 556 }; 557 opp-134000000 { 558 opp-hz = /bits/ 64 <134000000>; 559 }; 560 }; 561 562 bus_peri_opp_table: opp-table6 { 563 compatible = "operating-points-v2"; 564 565 opp-50000000 { 566 opp-hz = /bits/ 64 <50000000>; 567 }; 568 opp-100000000 { 569 opp-hz = /bits/ 64 <100000000>; 570 }; 571 }; 572 }; 573}; 574 575&combiner { 576 samsung,combiner-nr = <20>; 577 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 597}; 598 599&camera { 600 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 601 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 602 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 603 604 /* fimc_[0-3] are configured outside, under phandles */ 605 fimc_lite_0: fimc-lite@12390000 { 606 compatible = "samsung,exynos4212-fimc-lite"; 607 reg = <0x12390000 0x1000>; 608 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 609 power-domains = <&pd_isp>; 610 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; 611 clock-names = "flite"; 612 iommus = <&sysmmu_fimc_lite0>; 613 status = "disabled"; 614 }; 615 616 fimc_lite_1: fimc-lite@123a0000 { 617 compatible = "samsung,exynos4212-fimc-lite"; 618 reg = <0x123A0000 0x1000>; 619 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 620 power-domains = <&pd_isp>; 621 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; 622 clock-names = "flite"; 623 iommus = <&sysmmu_fimc_lite1>; 624 status = "disabled"; 625 }; 626 627 fimc_is: fimc-is@12000000 { 628 compatible = "samsung,exynos4212-fimc-is"; 629 reg = <0x12000000 0x260000>; 630 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 632 power-domains = <&pd_isp>; 633 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, 634 <&isp_clock CLK_ISP_FIMC_LITE1>, 635 <&isp_clock CLK_ISP_PPMUISPX>, 636 <&isp_clock CLK_ISP_PPMUISPMX>, 637 <&isp_clock CLK_ISP_FIMC_ISP>, 638 <&isp_clock CLK_ISP_FIMC_DRC>, 639 <&isp_clock CLK_ISP_FIMC_FD>, 640 <&isp_clock CLK_ISP_MCUISP>, 641 <&isp_clock CLK_ISP_GICISP>, 642 <&isp_clock CLK_ISP_MCUCTL_ISP>, 643 <&isp_clock CLK_ISP_PWM_ISP>, 644 <&isp_clock CLK_ISP_DIV_ISP0>, 645 <&isp_clock CLK_ISP_DIV_ISP1>, 646 <&isp_clock CLK_ISP_DIV_MCUISP0>, 647 <&isp_clock CLK_ISP_DIV_MCUISP1>, 648 <&clock CLK_MOUT_MPLL_USER_T>, 649 <&clock CLK_ACLK200>, 650 <&clock CLK_ACLK400_MCUISP>, 651 <&clock CLK_DIV_ACLK200>, 652 <&clock CLK_DIV_ACLK400_MCUISP>, 653 <&clock CLK_UART_ISP_SCLK>; 654 clock-names = "lite0", "lite1", "ppmuispx", 655 "ppmuispmx", "isp", 656 "drc", "fd", "mcuisp", 657 "gicisp", "mcuctl_isp", "pwm_isp", 658 "ispdiv0", "ispdiv1", "mcuispdiv0", 659 "mcuispdiv1", "mpll", "aclk200", 660 "aclk400mcuisp", "div_aclk200", 661 "div_aclk400mcuisp", "uart"; 662 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 663 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 664 iommu-names = "isp", "drc", "fd", "mcuctl"; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 ranges; 668 status = "disabled"; 669 670 pmu@10020000 { 671 reg = <0x10020000 0x3000>; 672 }; 673 674 i2c1_isp: i2c-isp@12140000 { 675 compatible = "samsung,exynos4212-i2c-isp"; 676 reg = <0x12140000 0x100>; 677 clocks = <&isp_clock CLK_ISP_I2C1_ISP>; 678 clock-names = "i2c_isp"; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 }; 682 }; 683}; 684 685&exynos_usbphy { 686 compatible = "samsung,exynos4x12-usb2-phy"; 687 samsung,sysreg-phandle = <&sys_reg>; 688}; 689 690&fimc_0 { 691 compatible = "samsung,exynos4212-fimc"; 692 samsung,pix-limits = <4224 8192 1920 4224>; 693 samsung,mainscaler-ext; 694 samsung,isp-wb; 695 samsung,cam-if; 696}; 697 698&fimc_1 { 699 compatible = "samsung,exynos4212-fimc"; 700 samsung,pix-limits = <4224 8192 1920 4224>; 701 samsung,mainscaler-ext; 702 samsung,isp-wb; 703 samsung,cam-if; 704}; 705 706&fimc_2 { 707 compatible = "samsung,exynos4212-fimc"; 708 samsung,pix-limits = <4224 8192 1920 4224>; 709 samsung,mainscaler-ext; 710 samsung,isp-wb; 711 samsung,lcd-wb; 712 samsung,cam-if; 713}; 714 715&fimc_3 { 716 compatible = "samsung,exynos4212-fimc"; 717 samsung,pix-limits = <1920 8192 1366 1920>; 718 samsung,rotators = <0>; 719 samsung,mainscaler-ext; 720 samsung,isp-wb; 721 samsung,lcd-wb; 722}; 723 724&gic { 725 cpu-offset = <0x4000>; 726}; 727 728&gpu { 729 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "gp", 741 "gpmmu", 742 "pp0", 743 "ppmmu0", 744 "pp1", 745 "ppmmu1", 746 "pp2", 747 "ppmmu2", 748 "pp3", 749 "ppmmu3", 750 "pmu"; 751 operating-points-v2 = <&gpu_opp_table>; 752 753 gpu_opp_table: opp-table { 754 compatible = "operating-points-v2"; 755 756 opp-160000000 { 757 opp-hz = /bits/ 64 <160000000>; 758 opp-microvolt = <875000>; 759 }; 760 opp-267000000 { 761 opp-hz = /bits/ 64 <267000000>; 762 opp-microvolt = <900000>; 763 }; 764 opp-350000000 { 765 opp-hz = /bits/ 64 <350000000>; 766 opp-microvolt = <950000>; 767 }; 768 opp-440000000 { 769 opp-hz = /bits/ 64 <440000000>; 770 opp-microvolt = <1025000>; 771 }; 772 }; 773}; 774 775&hdmi { 776 compatible = "samsung,exynos4212-hdmi"; 777}; 778 779&jpeg_codec { 780 compatible = "samsung,exynos4212-jpeg"; 781}; 782 783&rotator { 784 compatible = "samsung,exynos4212-rotator"; 785}; 786 787&mixer { 788 compatible = "samsung,exynos4212-mixer"; 789 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; 790 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 791 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; 792 interconnects = <&bus_display &bus_dmc>; 793}; 794 795&pmu { 796 interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 797 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 798 status = "okay"; 799}; 800 801&pmu_system_controller { 802 compatible = "samsung,exynos4412-pmu", "syscon"; 803 clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 804 "clkout4", "clkout8", "clkout9"; 805 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 806 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 807 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 808 #clock-cells = <1>; 809}; 810 811&tmu { 812 compatible = "samsung,exynos4412-tmu"; 813 interrupt-parent = <&combiner>; 814 interrupts = <2 4>; 815 reg = <0x100C0000 0x100>; 816 clocks = <&clock 383>; 817 clock-names = "tmu_apbif"; 818 status = "disabled"; 819}; 820 821#include "exynos4412-pinctrl.dtsi" 822