1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef FLOWCTRL_H 9 #define FLOWCTRL_H 10 11 #include <lib/mmio.h> 12 13 #include <stdbool.h> 14 15 #include <tegra_def.h> 16 17 #define FLOWCTRL_HALT_CPU0_EVENTS (0x0U) 18 #define FLOWCTRL_WAITEVENT (2U << 29) 19 #define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29) 20 #define FLOWCTRL_JTAG_RESUME (1U << 28) 21 #define FLOWCTRL_HALT_SCLK (1U << 27) 22 #define FLOWCTRL_HALT_LIC_IRQ (1U << 11) 23 #define FLOWCTRL_HALT_LIC_FIQ (1U << 10) 24 #define FLOWCTRL_HALT_GIC_IRQ (1U << 9) 25 #define FLOWCTRL_HALT_GIC_FIQ (1U << 8) 26 #define FLOWCTRL_HALT_BPMP_EVENTS (0x4U) 27 #define FLOWCTRL_CPU0_CSR (0x8U) 28 #define FLOWCTRL_CSR_HALT_MASK (1U << 22) 29 #define FLOWCTRL_CSR_PWR_OFF_STS (1U << 16) 30 #define FLOWCTRL_CSR_INTR_FLAG (1U << 15) 31 #define FLOWCTRL_CSR_EVENT_FLAG (1U << 14) 32 #define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3) 33 #define FLOWCTRL_CSR_ENABLE (1U << 0) 34 #define FLOWCTRL_HALT_CPU1_EVENTS (0x14U) 35 #define FLOWCTRL_CPU1_CSR (0x18U) 36 #define FLOW_CTLR_FLOW_DBG_QUAL (0x50U) 37 #define FLOWCTRL_FIQ2CCPLEX_ENABLE (1U << 28) 38 #define FLOWCTRL_FC_SEQ_INTERCEPT (0x5cU) 39 #define INTERCEPT_IRQ_PENDING (0xffU) 40 #define INTERCEPT_HVC (U(1) << 21) 41 #define INTERCEPT_ENTRY_CC4 (U(1) << 20) 42 #define INTERCEPT_ENTRY_PG_NONCPU (U(1) << 19) 43 #define INTERCEPT_EXIT_PG_NONCPU (U(1) << 18) 44 #define INTERCEPT_ENTRY_RG_CPU (U(1) << 17) 45 #define INTERCEPT_EXIT_RG_CPU (U(1) << 16) 46 #define INTERCEPT_ENTRY_PG_CORE0 (U(1) << 15) 47 #define INTERCEPT_EXIT_PG_CORE0 (U(1) << 14) 48 #define INTERCEPT_ENTRY_PG_CORE1 (U(1) << 13) 49 #define INTERCEPT_EXIT_PG_CORE1 (U(1) << 12) 50 #define INTERCEPT_ENTRY_PG_CORE2 (U(1) << 11) 51 #define INTERCEPT_EXIT_PG_CORE2 (U(1) << 10) 52 #define INTERCEPT_ENTRY_PG_CORE3 (U(1) << 9) 53 #define INTERCEPT_EXIT_PG_CORE3 (U(1) << 8) 54 #define INTERRUPT_PENDING_NONCPU (U(1) << 7) 55 #define INTERRUPT_PENDING_CRAIL (U(1) << 6) 56 #define INTERRUPT_PENDING_CORE0 (U(1) << 5) 57 #define INTERRUPT_PENDING_CORE1 (U(1) << 4) 58 #define INTERRUPT_PENDING_CORE2 (U(1) << 3) 59 #define INTERRUPT_PENDING_CORE3 (U(1) << 2) 60 #define CC4_INTERRUPT_PENDING (U(1) << 1) 61 #define HVC_INTERRUPT_PENDING (U(1) << 0) 62 #define FLOWCTRL_CC4_CORE0_CTRL (0x6cU) 63 #define FLOWCTRL_WAIT_WFI_BITMAP (0x100U) 64 #define FLOWCTRL_L2_FLUSH_CONTROL (0x94U) 65 #define FLOWCTRL_BPMP_CLUSTER_CONTROL (0x98U) 66 #define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2) 67 68 #define FLOWCTRL_ENABLE_EXT 12U 69 #define FLOWCTRL_ENABLE_EXT_MASK 3U 70 #define FLOWCTRL_PG_CPU_NONCPU 0x1U 71 #define FLOWCTRL_TURNOFF_CPURAIL 0x2U 72 tegra_fc_read_32(uint32_t off)73static inline uint32_t tegra_fc_read_32(uint32_t off) 74 { 75 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); 76 } 77 tegra_fc_write_32(uint32_t off,uint32_t val)78static inline void tegra_fc_write_32(uint32_t off, uint32_t val) 79 { 80 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); 81 } 82 83 void tegra_fc_bpmp_on(uint32_t entrypoint); 84 void tegra_fc_bpmp_off(void); 85 void tegra_fc_ccplex_pgexit_lock(void); 86 void tegra_fc_ccplex_pgexit_unlock(void); 87 void tegra_fc_cluster_idle(uint32_t midr); 88 void tegra_fc_cpu_powerdn(uint32_t mpidr); 89 void tegra_fc_cluster_powerdn(uint32_t midr); 90 void tegra_fc_cpu_on(int cpu); 91 void tegra_fc_cpu_off(int cpu); 92 void tegra_fc_disable_fiq_to_ccplex_routing(void); 93 void tegra_fc_enable_fiq_to_ccplex_routing(void); 94 bool tegra_fc_is_ccx_allowed(void); 95 void tegra_fc_lock_active_cluster(void); 96 void tegra_fc_soc_powerdn(uint32_t midr); 97 98 #endif /* FLOWCTRL_H */ 99