1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd.
4 *
5 * ARMv8 Foundation model DTS
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/memreserve/ 0x80000000 0x00010000;
13
14/ {
15	model = "Foundation-v8A";
16	compatible = "arm,foundation-aarch64", "arm,vexpress";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	aliases {
24		serial0 = &v2m_serial0;
25		serial2 = &v2m_serial2;
26		serial3 = &v2m_serial3;
27	};
28
29	ftpm {
30	        compatible = "microsoft,ftpm";
31	};
32
33	cpus {
34		#address-cells = <2>;
35		#size-cells = <0>;
36
37		cpu0: cpu@0 {
38			device_type = "cpu";
39			compatible = "arm,armv8";
40			reg = <0x0 0x0>;
41			next-level-cache = <&L2_0>;
42		};
43		cpu1: cpu@1 {
44			device_type = "cpu";
45			compatible = "arm,armv8";
46			reg = <0x0 0x1>;
47			next-level-cache = <&L2_0>;
48		};
49		cpu2: cpu@2 {
50			device_type = "cpu";
51			compatible = "arm,armv8";
52			reg = <0x0 0x2>;
53			next-level-cache = <&L2_0>;
54		};
55		cpu3: cpu@3 {
56			device_type = "cpu";
57			compatible = "arm,armv8";
58			reg = <0x0 0x3>;
59			next-level-cache = <&L2_0>;
60		};
61
62		L2_0: l2-cache0 {
63			compatible = "cache";
64		};
65	};
66
67	memory@80000000 {
68		device_type = "memory";
69		reg = <0x00000000 0x80000000 0 0x80000000>,
70		      <0x00000008 0x80000000 0 0x80000000>;
71	};
72
73	reserved-memory {
74		#address-cells = <2>;
75		#size-cells = <2>;
76		ranges;
77
78		optee@0x83000000 {
79			reg = <0x00000000 0x83000000 0 0x01000000>;
80			no-map;
81		};
82	};
83
84	timer {
85		compatible = "arm,armv8-timer";
86		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
90		clock-frequency = <100000000>;
91	};
92
93	pmu {
94		compatible = "arm,armv8-pmuv3";
95		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
96			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
97			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
98			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
99	};
100
101	watchdog@2a440000 {
102		compatible = "arm,sbsa-gwdt";
103		reg = <0x0 0x2a440000 0 0x1000>,
104			<0x0 0x2a450000 0 0x1000>;
105		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
106		timeout-sec = <30>;
107	};
108
109	v2m_clk24mhz: clk24mhz {
110		compatible = "fixed-clock";
111		#clock-cells = <0>;
112		clock-frequency = <24000000>;
113		clock-output-names = "v2m:clk24mhz";
114	};
115
116	v2m_refclk1mhz: refclk1mhz {
117		compatible = "fixed-clock";
118		#clock-cells = <0>;
119		clock-frequency = <1000000>;
120		clock-output-names = "v2m:refclk1mhz";
121	};
122
123	v2m_refclk32khz: refclk32khz {
124		compatible = "fixed-clock";
125		#clock-cells = <0>;
126		clock-frequency = <32768>;
127		clock-output-names = "v2m:refclk32khz";
128	};
129
130	bus@8000000 {
131		compatible = "arm,vexpress,v2m-p1", "simple-bus";
132		#address-cells = <2>; /* SMB chipselect number and offset */
133		#size-cells = <1>;
134
135		ranges = <0 0 0 0x08000000 0x04000000>,
136			 <1 0 0 0x14000000 0x04000000>,
137			 <2 0 0 0x18000000 0x04000000>,
138			 <3 0 0 0x1c000000 0x04000000>,
139			 <4 0 0 0x0c000000 0x04000000>,
140			 <5 0 0 0x10000000 0x04000000>;
141
142		#interrupt-cells = <1>;
143		interrupt-map-mask = <0 0 63>;
144		interrupt-map = <0 0  0 &gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
145				<0 0  1 &gic 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
146				<0 0  2 &gic 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
147				<0 0  3 &gic 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
148				<0 0  4 &gic 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
149				<0 0  5 &gic 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
150				<0 0  6 &gic 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
151				<0 0  7 &gic 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
152				<0 0  8 &gic 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
153				<0 0  9 &gic 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
154				<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
155				<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
156				<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
157				<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
158				<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
159				<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
160				<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
161				<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
162				<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
163				<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
164				<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
165				<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
166				<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
167				<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
168				<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
169				<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
170				<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
171				<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
172				<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
173				<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
174				<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
175				<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
176				<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
177				<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
178				<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
179				<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
180				<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
181				<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
182				<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
183				<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
184				<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
185				<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
186				<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
187
188		ethernet@202000000 {
189			compatible = "smsc,lan91c111";
190			reg = <2 0x02000000 0x10000>;
191			interrupts = <15>;
192		};
193
194		iofpga-bus@300000000 {
195			compatible = "simple-bus";
196			#address-cells = <1>;
197			#size-cells = <1>;
198			ranges = <0 3 0 0x200000>;
199
200			v2m_sysreg: sysreg@10000 {
201				compatible = "arm,vexpress-sysreg";
202				reg = <0x010000 0x1000>;
203			};
204
205			v2m_serial0: serial@90000 {
206				compatible = "arm,pl011", "arm,primecell";
207				reg = <0x090000 0x1000>;
208				interrupts = <5>;
209				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
210				clock-names = "uartclk", "apb_pclk";
211			};
212
213			v2m_serial2: serial@b0000 {
214				compatible = "arm,pl011", "arm,primecell";
215				reg = <0x0b0000 0x1000>;
216				interrupts = <7>;
217				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
218				clock-names = "uartclk", "apb_pclk";
219			};
220
221			v2m_serial3: serial@c0000 {
222				compatible = "arm,pl011", "arm,primecell";
223				reg = <0x0c0000 0x1000>;
224				interrupts = <8>;
225				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
226				clock-names = "uartclk", "apb_pclk";
227			};
228
229			virtio-block@130000 {
230				compatible = "virtio,mmio";
231				reg = <0x130000 0x200>;
232				interrupts = <42>;
233			};
234		};
235	};
236
237	firmware {
238		optee {
239			compatible = "linaro,optee-tz";
240			method = "smc";
241		};
242	};
243
244};
245