1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 next-level-cache = <&l2>; 32 cpu-idle-states = <&CPU_PW20>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@1 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a72"; 39 reg = <0x1>; 40 enable-method = "psci"; 41 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PW20>; 44 #cooling-cells = <2>; 45 }; 46 47 l2: l2-cache { 48 compatible = "cache"; 49 }; 50 }; 51 52 idle-states { 53 /* 54 * PSCI node is not added default, U-boot will add missing 55 * parts if it determines to use PSCI. 56 */ 57 entry-method = "psci"; 58 59 CPU_PW20: cpu-pw20 { 60 compatible = "arm,idle-state"; 61 idle-state-name = "PW20"; 62 arm,psci-suspend-param = <0x0>; 63 entry-latency-us = <2000>; 64 exit-latency-us = <2000>; 65 min-residency-us = <6000>; 66 }; 67 }; 68 69 sysclk: sysclk { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <100000000>; 73 clock-output-names = "sysclk"; 74 }; 75 76 osc_27m: clock-osc-27m { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <27000000>; 80 clock-output-names = "phy_27m"; 81 }; 82 83 firmware { 84 optee: optee { 85 compatible = "linaro,optee-tz"; 86 method = "smc"; 87 status = "disabled"; 88 }; 89 }; 90 91 reboot { 92 compatible ="syscon-reboot"; 93 regmap = <&rst>; 94 offset = <0>; 95 mask = <0x02>; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 101 IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 103 IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 105 IRQ_TYPE_LEVEL_LOW)>, 106 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 107 IRQ_TYPE_LEVEL_LOW)>; 108 }; 109 110 pmu { 111 compatible = "arm,cortex-a72-pmu"; 112 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 113 }; 114 115 gic: interrupt-controller@6000000 { 116 compatible= "arm,gic-v3"; 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 121 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 122 #interrupt-cells= <3>; 123 interrupt-controller; 124 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 125 IRQ_TYPE_LEVEL_LOW)>; 126 its: gic-its@6020000 { 127 compatible = "arm,gic-v3-its"; 128 msi-controller; 129 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 130 }; 131 }; 132 133 thermal-zones { 134 ddr-controller { 135 polling-delay-passive = <1000>; 136 polling-delay = <5000>; 137 thermal-sensors = <&tmu 0>; 138 139 trips { 140 ddr-ctrler-alert { 141 temperature = <85000>; 142 hysteresis = <2000>; 143 type = "passive"; 144 }; 145 146 ddr-ctrler-crit { 147 temperature = <95000>; 148 hysteresis = <2000>; 149 type = "critical"; 150 }; 151 }; 152 }; 153 154 core-cluster { 155 polling-delay-passive = <1000>; 156 polling-delay = <5000>; 157 thermal-sensors = <&tmu 1>; 158 159 trips { 160 core_cluster_alert: core-cluster-alert { 161 temperature = <85000>; 162 hysteresis = <2000>; 163 type = "passive"; 164 }; 165 166 core_cluster_crit: core-cluster-crit { 167 temperature = <95000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 173 cooling-maps { 174 map0 { 175 trip = <&core_cluster_alert>; 176 cooling-device = 177 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 178 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 179 }; 180 }; 181 }; 182 }; 183 184 soc: soc { 185 compatible = "simple-bus"; 186 #address-cells = <2>; 187 #size-cells = <2>; 188 ranges; 189 190 ddr: memory-controller@1080000 { 191 compatible = "fsl,qoriq-memory-controller"; 192 reg = <0x0 0x1080000 0x0 0x1000>; 193 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 194 little-endian; 195 }; 196 197 dcfg: syscon@1e00000 { 198 #address-cells = <1>; 199 #size-cells = <1>; 200 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 201 reg = <0x0 0x1e00000 0x0 0x10000>; 202 ranges = <0x0 0x0 0x1e00000 0x10000>; 203 little-endian; 204 205 fspi_clk: clock-controller@900 { 206 compatible = "fsl,ls1028a-flexspi-clk"; 207 reg = <0x900 0x4>; 208 #clock-cells = <0>; 209 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 210 clock-output-names = "fspi_clk"; 211 }; 212 }; 213 214 rst: syscon@1e60000 { 215 compatible = "syscon"; 216 reg = <0x0 0x1e60000 0x0 0x10000>; 217 little-endian; 218 }; 219 220 scfg: syscon@1fc0000 { 221 compatible = "fsl,ls1028a-scfg", "syscon"; 222 reg = <0x0 0x1fc0000 0x0 0x10000>; 223 big-endian; 224 }; 225 226 clockgen: clock-controller@1300000 { 227 compatible = "fsl,ls1028a-clockgen"; 228 reg = <0x0 0x1300000 0x0 0xa0000>; 229 #clock-cells = <2>; 230 clocks = <&sysclk>; 231 }; 232 233 i2c0: i2c@2000000 { 234 compatible = "fsl,vf610-i2c"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 reg = <0x0 0x2000000 0x0 0x10000>; 238 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 240 QORIQ_CLK_PLL_DIV(4)>; 241 status = "disabled"; 242 }; 243 244 i2c1: i2c@2010000 { 245 compatible = "fsl,vf610-i2c"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <0x0 0x2010000 0x0 0x10000>; 249 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 251 QORIQ_CLK_PLL_DIV(4)>; 252 status = "disabled"; 253 }; 254 255 i2c2: i2c@2020000 { 256 compatible = "fsl,vf610-i2c"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 reg = <0x0 0x2020000 0x0 0x10000>; 260 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 262 QORIQ_CLK_PLL_DIV(4)>; 263 status = "disabled"; 264 }; 265 266 i2c3: i2c@2030000 { 267 compatible = "fsl,vf610-i2c"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 reg = <0x0 0x2030000 0x0 0x10000>; 271 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 273 QORIQ_CLK_PLL_DIV(4)>; 274 status = "disabled"; 275 }; 276 277 i2c4: i2c@2040000 { 278 compatible = "fsl,vf610-i2c"; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 reg = <0x0 0x2040000 0x0 0x10000>; 282 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 284 QORIQ_CLK_PLL_DIV(4)>; 285 status = "disabled"; 286 }; 287 288 i2c5: i2c@2050000 { 289 compatible = "fsl,vf610-i2c"; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <0x0 0x2050000 0x0 0x10000>; 293 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 295 QORIQ_CLK_PLL_DIV(4)>; 296 status = "disabled"; 297 }; 298 299 i2c6: i2c@2060000 { 300 compatible = "fsl,vf610-i2c"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg = <0x0 0x2060000 0x0 0x10000>; 304 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 306 QORIQ_CLK_PLL_DIV(4)>; 307 status = "disabled"; 308 }; 309 310 i2c7: i2c@2070000 { 311 compatible = "fsl,vf610-i2c"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x0 0x2070000 0x0 0x10000>; 315 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 317 QORIQ_CLK_PLL_DIV(4)>; 318 status = "disabled"; 319 }; 320 321 fspi: spi@20c0000 { 322 compatible = "nxp,lx2160a-fspi"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 reg = <0x0 0x20c0000 0x0 0x10000>, 326 <0x0 0x20000000 0x0 0x10000000>; 327 reg-names = "fspi_base", "fspi_mmap"; 328 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&fspi_clk>, <&fspi_clk>; 330 clock-names = "fspi_en", "fspi"; 331 status = "disabled"; 332 }; 333 334 dspi0: spi@2100000 { 335 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 reg = <0x0 0x2100000 0x0 0x10000>; 339 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 340 clock-names = "dspi"; 341 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 342 QORIQ_CLK_PLL_DIV(2)>; 343 dmas = <&edma0 0 62>, <&edma0 0 60>; 344 dma-names = "tx", "rx"; 345 spi-num-chipselects = <4>; 346 little-endian; 347 status = "disabled"; 348 }; 349 350 dspi1: spi@2110000 { 351 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 reg = <0x0 0x2110000 0x0 0x10000>; 355 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 356 clock-names = "dspi"; 357 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 358 QORIQ_CLK_PLL_DIV(2)>; 359 dmas = <&edma0 0 58>, <&edma0 0 56>; 360 dma-names = "tx", "rx"; 361 spi-num-chipselects = <4>; 362 little-endian; 363 status = "disabled"; 364 }; 365 366 dspi2: spi@2120000 { 367 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <0x0 0x2120000 0x0 0x10000>; 371 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 372 clock-names = "dspi"; 373 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 374 QORIQ_CLK_PLL_DIV(2)>; 375 dmas = <&edma0 0 54>, <&edma0 0 2>; 376 dma-names = "tx", "rx"; 377 spi-num-chipselects = <3>; 378 little-endian; 379 status = "disabled"; 380 }; 381 382 esdhc: mmc@2140000 { 383 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 384 reg = <0x0 0x2140000 0x0 0x10000>; 385 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 386 clock-frequency = <0>; /* fixed up by bootloader */ 387 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 388 voltage-ranges = <1800 1800 3300 3300>; 389 sdhci,auto-cmd12; 390 little-endian; 391 bus-width = <4>; 392 status = "disabled"; 393 }; 394 395 esdhc1: mmc@2150000 { 396 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 397 reg = <0x0 0x2150000 0x0 0x10000>; 398 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 399 clock-frequency = <0>; /* fixed up by bootloader */ 400 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 401 voltage-ranges = <1800 1800>; 402 sdhci,auto-cmd12; 403 non-removable; 404 little-endian; 405 bus-width = <4>; 406 status = "disabled"; 407 }; 408 409 can0: can@2180000 { 410 compatible = "fsl,lx2160ar1-flexcan"; 411 reg = <0x0 0x2180000 0x0 0x10000>; 412 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 414 QORIQ_CLK_PLL_DIV(2)>, 415 <&clockgen QORIQ_CLK_PLATFORM_PLL 416 QORIQ_CLK_PLL_DIV(2)>; 417 clock-names = "ipg", "per"; 418 status = "disabled"; 419 }; 420 421 can1: can@2190000 { 422 compatible = "fsl,lx2160ar1-flexcan"; 423 reg = <0x0 0x2190000 0x0 0x10000>; 424 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 426 QORIQ_CLK_PLL_DIV(2)>, 427 <&clockgen QORIQ_CLK_PLATFORM_PLL 428 QORIQ_CLK_PLL_DIV(2)>; 429 clock-names = "ipg", "per"; 430 status = "disabled"; 431 }; 432 433 duart0: serial@21c0500 { 434 compatible = "fsl,ns16550", "ns16550a"; 435 reg = <0x00 0x21c0500 0x0 0x100>; 436 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 438 QORIQ_CLK_PLL_DIV(2)>; 439 status = "disabled"; 440 }; 441 442 duart1: serial@21c0600 { 443 compatible = "fsl,ns16550", "ns16550a"; 444 reg = <0x00 0x21c0600 0x0 0x100>; 445 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 447 QORIQ_CLK_PLL_DIV(2)>; 448 status = "disabled"; 449 }; 450 451 452 lpuart0: serial@2260000 { 453 compatible = "fsl,ls1028a-lpuart"; 454 reg = <0x0 0x2260000 0x0 0x1000>; 455 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 457 QORIQ_CLK_PLL_DIV(2)>; 458 clock-names = "ipg"; 459 dma-names = "rx","tx"; 460 dmas = <&edma0 1 32>, 461 <&edma0 1 33>; 462 status = "disabled"; 463 }; 464 465 lpuart1: serial@2270000 { 466 compatible = "fsl,ls1028a-lpuart"; 467 reg = <0x0 0x2270000 0x0 0x1000>; 468 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 470 QORIQ_CLK_PLL_DIV(2)>; 471 clock-names = "ipg"; 472 dma-names = "rx","tx"; 473 dmas = <&edma0 1 30>, 474 <&edma0 1 31>; 475 status = "disabled"; 476 }; 477 478 lpuart2: serial@2280000 { 479 compatible = "fsl,ls1028a-lpuart"; 480 reg = <0x0 0x2280000 0x0 0x1000>; 481 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 483 QORIQ_CLK_PLL_DIV(2)>; 484 clock-names = "ipg"; 485 dma-names = "rx","tx"; 486 dmas = <&edma0 1 28>, 487 <&edma0 1 29>; 488 status = "disabled"; 489 }; 490 491 lpuart3: serial@2290000 { 492 compatible = "fsl,ls1028a-lpuart"; 493 reg = <0x0 0x2290000 0x0 0x1000>; 494 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 496 QORIQ_CLK_PLL_DIV(2)>; 497 clock-names = "ipg"; 498 dma-names = "rx","tx"; 499 dmas = <&edma0 1 26>, 500 <&edma0 1 27>; 501 status = "disabled"; 502 }; 503 504 lpuart4: serial@22a0000 { 505 compatible = "fsl,ls1028a-lpuart"; 506 reg = <0x0 0x22a0000 0x0 0x1000>; 507 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 509 QORIQ_CLK_PLL_DIV(2)>; 510 clock-names = "ipg"; 511 dma-names = "rx","tx"; 512 dmas = <&edma0 1 24>, 513 <&edma0 1 25>; 514 status = "disabled"; 515 }; 516 517 lpuart5: serial@22b0000 { 518 compatible = "fsl,ls1028a-lpuart"; 519 reg = <0x0 0x22b0000 0x0 0x1000>; 520 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 522 QORIQ_CLK_PLL_DIV(2)>; 523 clock-names = "ipg"; 524 dma-names = "rx","tx"; 525 dmas = <&edma0 1 22>, 526 <&edma0 1 23>; 527 status = "disabled"; 528 }; 529 530 edma0: dma-controller@22c0000 { 531 #dma-cells = <2>; 532 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 533 reg = <0x0 0x22c0000 0x0 0x10000>, 534 <0x0 0x22d0000 0x0 0x10000>, 535 <0x0 0x22e0000 0x0 0x10000>; 536 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 538 interrupt-names = "edma-tx", "edma-err"; 539 dma-channels = <32>; 540 clock-names = "dmamux0", "dmamux1"; 541 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 542 QORIQ_CLK_PLL_DIV(2)>, 543 <&clockgen QORIQ_CLK_PLATFORM_PLL 544 QORIQ_CLK_PLL_DIV(2)>; 545 }; 546 547 gpio1: gpio@2300000 { 548 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 549 reg = <0x0 0x2300000 0x0 0x10000>; 550 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 little-endian; 556 }; 557 558 gpio2: gpio@2310000 { 559 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 560 reg = <0x0 0x2310000 0x0 0x10000>; 561 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 little-endian; 567 }; 568 569 gpio3: gpio@2320000 { 570 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 571 reg = <0x0 0x2320000 0x0 0x10000>; 572 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 573 gpio-controller; 574 #gpio-cells = <2>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 little-endian; 578 }; 579 580 usb0: usb@3100000 { 581 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 582 reg = <0x0 0x3100000 0x0 0x10000>; 583 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 584 dr_mode = "host"; 585 snps,dis_rxdet_inp3_quirk; 586 snps,quirk-frame-length-adjustment = <0x20>; 587 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 588 status = "disabled"; 589 }; 590 591 usb1: usb@3110000 { 592 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 593 reg = <0x0 0x3110000 0x0 0x10000>; 594 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 595 dr_mode = "host"; 596 snps,dis_rxdet_inp3_quirk; 597 snps,quirk-frame-length-adjustment = <0x20>; 598 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 599 status = "disabled"; 600 }; 601 602 sata: sata@3200000 { 603 compatible = "fsl,ls1028a-ahci"; 604 reg = <0x0 0x3200000 0x0 0x10000>, 605 <0x7 0x100520 0x0 0x4>; 606 reg-names = "ahci", "sata-ecc"; 607 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 609 QORIQ_CLK_PLL_DIV(2)>; 610 status = "disabled"; 611 }; 612 613 pcie1: pcie@3400000 { 614 compatible = "fsl,ls1028a-pcie"; 615 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 616 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 617 reg-names = "regs", "config"; 618 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 619 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 620 interrupt-names = "pme", "aer"; 621 #address-cells = <3>; 622 #size-cells = <2>; 623 device_type = "pci"; 624 dma-coherent; 625 num-viewport = <8>; 626 bus-range = <0x0 0xff>; 627 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 628 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 629 msi-parent = <&its>; 630 #interrupt-cells = <1>; 631 interrupt-map-mask = <0 0 0 7>; 632 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 633 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 634 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 635 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 636 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 637 status = "disabled"; 638 }; 639 640 pcie2: pcie@3500000 { 641 compatible = "fsl,ls1028a-pcie"; 642 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 643 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 644 reg-names = "regs", "config"; 645 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "pme", "aer"; 648 #address-cells = <3>; 649 #size-cells = <2>; 650 device_type = "pci"; 651 dma-coherent; 652 num-viewport = <8>; 653 bus-range = <0x0 0xff>; 654 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 655 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 656 msi-parent = <&its>; 657 #interrupt-cells = <1>; 658 interrupt-map-mask = <0 0 0 7>; 659 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 660 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 661 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 662 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 663 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 664 status = "disabled"; 665 }; 666 667 smmu: iommu@5000000 { 668 compatible = "arm,mmu-500"; 669 reg = <0 0x5000000 0 0x800000>; 670 #global-interrupts = <8>; 671 #iommu-cells = <1>; 672 stream-match-mask = <0x7c00>; 673 /* global secure fault */ 674 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 675 /* combined secure interrupt */ 676 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 677 /* global non-secure fault */ 678 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 679 /* combined non-secure interrupt */ 680 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 681 /* performance counter interrupts 0-7 */ 682 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 684 /* per context interrupt, 64 interrupts */ 685 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 717 }; 718 719 crypto: crypto@8000000 { 720 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 721 fsl,sec-era = <10>; 722 #address-cells = <1>; 723 #size-cells = <1>; 724 ranges = <0x0 0x00 0x8000000 0x100000>; 725 reg = <0x00 0x8000000 0x0 0x100000>; 726 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 727 dma-coherent; 728 729 sec_jr0: jr@10000 { 730 compatible = "fsl,sec-v5.0-job-ring", 731 "fsl,sec-v4.0-job-ring"; 732 reg = <0x10000 0x10000>; 733 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 734 }; 735 736 sec_jr1: jr@20000 { 737 compatible = "fsl,sec-v5.0-job-ring", 738 "fsl,sec-v4.0-job-ring"; 739 reg = <0x20000 0x10000>; 740 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 741 }; 742 743 sec_jr2: jr@30000 { 744 compatible = "fsl,sec-v5.0-job-ring", 745 "fsl,sec-v4.0-job-ring"; 746 reg = <0x30000 0x10000>; 747 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 748 }; 749 750 sec_jr3: jr@40000 { 751 compatible = "fsl,sec-v5.0-job-ring", 752 "fsl,sec-v4.0-job-ring"; 753 reg = <0x40000 0x10000>; 754 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 755 }; 756 }; 757 758 qdma: dma-controller@8380000 { 759 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 760 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 761 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 762 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 763 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-names = "qdma-error", "qdma-queue0", 769 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 770 dma-channels = <8>; 771 block-number = <1>; 772 block-offset = <0x10000>; 773 fsl,dma-queues = <2>; 774 status-sizes = <64>; 775 queue-sizes = <64 64>; 776 }; 777 778 cluster1_core0_watchdog: watchdog@c000000 { 779 compatible = "arm,sp805", "arm,primecell"; 780 reg = <0x0 0xc000000 0x0 0x1000>; 781 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 782 QORIQ_CLK_PLL_DIV(16)>, 783 <&clockgen QORIQ_CLK_PLATFORM_PLL 784 QORIQ_CLK_PLL_DIV(16)>; 785 clock-names = "wdog_clk", "apb_pclk"; 786 }; 787 788 cluster1_core1_watchdog: watchdog@c010000 { 789 compatible = "arm,sp805", "arm,primecell"; 790 reg = <0x0 0xc010000 0x0 0x1000>; 791 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 792 QORIQ_CLK_PLL_DIV(16)>, 793 <&clockgen QORIQ_CLK_PLATFORM_PLL 794 QORIQ_CLK_PLL_DIV(16)>; 795 clock-names = "wdog_clk", "apb_pclk"; 796 }; 797 798 malidp0: display@f080000 { 799 compatible = "arm,mali-dp500"; 800 reg = <0x0 0xf080000 0x0 0x10000>; 801 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 802 <0 223 IRQ_TYPE_LEVEL_HIGH>; 803 interrupt-names = "DE", "SE"; 804 clocks = <&dpclk>, 805 <&clockgen QORIQ_CLK_HWACCEL 2>, 806 <&clockgen QORIQ_CLK_HWACCEL 2>, 807 <&clockgen QORIQ_CLK_HWACCEL 2>; 808 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 809 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 810 arm,malidp-arqos-value = <0xd000d000>; 811 812 port { 813 dpi0_out: endpoint { 814 815 }; 816 }; 817 }; 818 819 gpu: gpu@f0c0000 { 820 compatible = "vivante,gc"; 821 reg = <0x0 0xf0c0000 0x0 0x10000>; 822 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 824 <&clockgen QORIQ_CLK_HWACCEL 2>, 825 <&clockgen QORIQ_CLK_HWACCEL 2>; 826 clock-names = "core", "shader", "bus"; 827 #cooling-cells = <2>; 828 }; 829 830 sai1: audio-controller@f100000 { 831 #sound-dai-cells = <0>; 832 compatible = "fsl,vf610-sai"; 833 reg = <0x0 0xf100000 0x0 0x10000>; 834 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 836 QORIQ_CLK_PLL_DIV(2)>, 837 <&clockgen QORIQ_CLK_PLATFORM_PLL 838 QORIQ_CLK_PLL_DIV(2)>, 839 <&clockgen QORIQ_CLK_PLATFORM_PLL 840 QORIQ_CLK_PLL_DIV(2)>, 841 <&clockgen QORIQ_CLK_PLATFORM_PLL 842 QORIQ_CLK_PLL_DIV(2)>; 843 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 844 dma-names = "tx", "rx"; 845 dmas = <&edma0 1 4>, 846 <&edma0 1 3>; 847 fsl,sai-asynchronous; 848 status = "disabled"; 849 }; 850 851 sai2: audio-controller@f110000 { 852 #sound-dai-cells = <0>; 853 compatible = "fsl,vf610-sai"; 854 reg = <0x0 0xf110000 0x0 0x10000>; 855 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 857 QORIQ_CLK_PLL_DIV(2)>, 858 <&clockgen QORIQ_CLK_PLATFORM_PLL 859 QORIQ_CLK_PLL_DIV(2)>, 860 <&clockgen QORIQ_CLK_PLATFORM_PLL 861 QORIQ_CLK_PLL_DIV(2)>, 862 <&clockgen QORIQ_CLK_PLATFORM_PLL 863 QORIQ_CLK_PLL_DIV(2)>; 864 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 865 dma-names = "tx", "rx"; 866 dmas = <&edma0 1 6>, 867 <&edma0 1 5>; 868 fsl,sai-asynchronous; 869 status = "disabled"; 870 }; 871 872 sai3: audio-controller@f120000 { 873 #sound-dai-cells = <0>; 874 compatible = "fsl,vf610-sai"; 875 reg = <0x0 0xf120000 0x0 0x10000>; 876 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 878 QORIQ_CLK_PLL_DIV(2)>, 879 <&clockgen QORIQ_CLK_PLATFORM_PLL 880 QORIQ_CLK_PLL_DIV(2)>, 881 <&clockgen QORIQ_CLK_PLATFORM_PLL 882 QORIQ_CLK_PLL_DIV(2)>, 883 <&clockgen QORIQ_CLK_PLATFORM_PLL 884 QORIQ_CLK_PLL_DIV(2)>; 885 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 886 dma-names = "tx", "rx"; 887 dmas = <&edma0 1 8>, 888 <&edma0 1 7>; 889 fsl,sai-asynchronous; 890 status = "disabled"; 891 }; 892 893 sai4: audio-controller@f130000 { 894 #sound-dai-cells = <0>; 895 compatible = "fsl,vf610-sai"; 896 reg = <0x0 0xf130000 0x0 0x10000>; 897 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 899 QORIQ_CLK_PLL_DIV(2)>, 900 <&clockgen QORIQ_CLK_PLATFORM_PLL 901 QORIQ_CLK_PLL_DIV(2)>, 902 <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(2)>, 904 <&clockgen QORIQ_CLK_PLATFORM_PLL 905 QORIQ_CLK_PLL_DIV(2)>; 906 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 907 dma-names = "tx", "rx"; 908 dmas = <&edma0 1 10>, 909 <&edma0 1 9>; 910 fsl,sai-asynchronous; 911 status = "disabled"; 912 }; 913 914 sai5: audio-controller@f140000 { 915 #sound-dai-cells = <0>; 916 compatible = "fsl,vf610-sai"; 917 reg = <0x0 0xf140000 0x0 0x10000>; 918 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 920 QORIQ_CLK_PLL_DIV(2)>, 921 <&clockgen QORIQ_CLK_PLATFORM_PLL 922 QORIQ_CLK_PLL_DIV(2)>, 923 <&clockgen QORIQ_CLK_PLATFORM_PLL 924 QORIQ_CLK_PLL_DIV(2)>, 925 <&clockgen QORIQ_CLK_PLATFORM_PLL 926 QORIQ_CLK_PLL_DIV(2)>; 927 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 928 dma-names = "tx", "rx"; 929 dmas = <&edma0 1 12>, 930 <&edma0 1 11>; 931 fsl,sai-asynchronous; 932 status = "disabled"; 933 }; 934 935 sai6: audio-controller@f150000 { 936 #sound-dai-cells = <0>; 937 compatible = "fsl,vf610-sai"; 938 reg = <0x0 0xf150000 0x0 0x10000>; 939 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 941 QORIQ_CLK_PLL_DIV(2)>, 942 <&clockgen QORIQ_CLK_PLATFORM_PLL 943 QORIQ_CLK_PLL_DIV(2)>, 944 <&clockgen QORIQ_CLK_PLATFORM_PLL 945 QORIQ_CLK_PLL_DIV(2)>, 946 <&clockgen QORIQ_CLK_PLATFORM_PLL 947 QORIQ_CLK_PLL_DIV(2)>; 948 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 949 dma-names = "tx", "rx"; 950 dmas = <&edma0 1 14>, 951 <&edma0 1 13>; 952 fsl,sai-asynchronous; 953 status = "disabled"; 954 }; 955 956 dpclk: clock-controller@f1f0000 { 957 compatible = "fsl,ls1028a-plldig"; 958 reg = <0x0 0xf1f0000 0x0 0x10000>; 959 #clock-cells = <0>; 960 clocks = <&osc_27m>; 961 }; 962 963 tmu: tmu@1f80000 { 964 compatible = "fsl,qoriq-tmu"; 965 reg = <0x0 0x1f80000 0x0 0x10000>; 966 interrupts = <0 23 0x4>; 967 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 968 fsl,tmu-calibration = <0x00000000 0x00000024 969 0x00000001 0x0000002b 970 0x00000002 0x00000031 971 0x00000003 0x00000038 972 0x00000004 0x0000003f 973 0x00000005 0x00000045 974 0x00000006 0x0000004c 975 0x00000007 0x00000053 976 0x00000008 0x00000059 977 0x00000009 0x00000060 978 0x0000000a 0x00000066 979 0x0000000b 0x0000006d 980 981 0x00010000 0x0000001c 982 0x00010001 0x00000024 983 0x00010002 0x0000002c 984 0x00010003 0x00000035 985 0x00010004 0x0000003d 986 0x00010005 0x00000045 987 0x00010006 0x0000004d 988 0x00010007 0x00000055 989 0x00010008 0x0000005e 990 0x00010009 0x00000066 991 0x0001000a 0x0000006e 992 993 0x00020000 0x00000018 994 0x00020001 0x00000022 995 0x00020002 0x0000002d 996 0x00020003 0x00000038 997 0x00020004 0x00000043 998 0x00020005 0x0000004d 999 0x00020006 0x00000058 1000 0x00020007 0x00000063 1001 0x00020008 0x0000006e 1002 1003 0x00030000 0x00000010 1004 0x00030001 0x0000001c 1005 0x00030002 0x00000029 1006 0x00030003 0x00000036 1007 0x00030004 0x00000042 1008 0x00030005 0x0000004f 1009 0x00030006 0x0000005b 1010 0x00030007 0x00000068>; 1011 little-endian; 1012 #thermal-sensor-cells = <1>; 1013 }; 1014 1015 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1016 compatible = "pci-host-ecam-generic"; 1017 reg = <0x01 0xf0000000 0x0 0x100000>; 1018 #address-cells = <3>; 1019 #size-cells = <2>; 1020 msi-parent = <&its>; 1021 device_type = "pci"; 1022 bus-range = <0x0 0x0>; 1023 dma-coherent; 1024 msi-map = <0 &its 0x17 0xe>; 1025 iommu-map = <0 &smmu 0x17 0xe>; 1026 /* PF0-6 BAR0 - non-prefetchable memory */ 1027 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1028 /* PF0-6 BAR2 - prefetchable memory */ 1029 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1030 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1031 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1032 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1033 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1034 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1035 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1036 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1037 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1038 /* BAR4 (PF5) - non-prefetchable memory */ 1039 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1040 1041 enetc_port0: ethernet@0,0 { 1042 compatible = "fsl,enetc"; 1043 reg = <0x000000 0 0 0 0>; 1044 status = "disabled"; 1045 }; 1046 1047 enetc_port1: ethernet@0,1 { 1048 compatible = "fsl,enetc"; 1049 reg = <0x000100 0 0 0 0>; 1050 status = "disabled"; 1051 }; 1052 1053 enetc_port2: ethernet@0,2 { 1054 compatible = "fsl,enetc"; 1055 reg = <0x000200 0 0 0 0>; 1056 phy-mode = "internal"; 1057 status = "disabled"; 1058 1059 fixed-link { 1060 speed = <2500>; 1061 full-duplex; 1062 pause; 1063 }; 1064 }; 1065 1066 enetc_mdio_pf3: mdio@0,3 { 1067 compatible = "fsl,enetc-mdio"; 1068 reg = <0x000300 0 0 0 0>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 }; 1072 1073 ethernet@0,4 { 1074 compatible = "fsl,enetc-ptp"; 1075 reg = <0x000400 0 0 0 0>; 1076 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1077 little-endian; 1078 fsl,extts-fifo; 1079 }; 1080 1081 mscc_felix: ethernet-switch@0,5 { 1082 reg = <0x000500 0 0 0 0>; 1083 /* IEP INT_B */ 1084 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1085 status = "disabled"; 1086 1087 ports { 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 /* External ports */ 1092 mscc_felix_port0: port@0 { 1093 reg = <0>; 1094 status = "disabled"; 1095 }; 1096 1097 mscc_felix_port1: port@1 { 1098 reg = <1>; 1099 status = "disabled"; 1100 }; 1101 1102 mscc_felix_port2: port@2 { 1103 reg = <2>; 1104 status = "disabled"; 1105 }; 1106 1107 mscc_felix_port3: port@3 { 1108 reg = <3>; 1109 status = "disabled"; 1110 }; 1111 1112 /* Internal ports */ 1113 mscc_felix_port4: port@4 { 1114 reg = <4>; 1115 phy-mode = "internal"; 1116 status = "disabled"; 1117 1118 fixed-link { 1119 speed = <2500>; 1120 full-duplex; 1121 pause; 1122 }; 1123 }; 1124 1125 mscc_felix_port5: port@5 { 1126 reg = <5>; 1127 phy-mode = "internal"; 1128 status = "disabled"; 1129 1130 fixed-link { 1131 speed = <1000>; 1132 full-duplex; 1133 pause; 1134 }; 1135 }; 1136 }; 1137 }; 1138 1139 enetc_port3: ethernet@0,6 { 1140 compatible = "fsl,enetc"; 1141 reg = <0x000600 0 0 0 0>; 1142 phy-mode = "internal"; 1143 status = "disabled"; 1144 1145 fixed-link { 1146 speed = <1000>; 1147 full-duplex; 1148 pause; 1149 }; 1150 }; 1151 1152 rcec@1f,0 { 1153 reg = <0x00f800 0 0 0 0>; 1154 /* IEP INT_A */ 1155 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1156 }; 1157 }; 1158 1159 /* Integrated Endpoint Register Block */ 1160 ierb@1f0800000 { 1161 compatible = "fsl,ls1028a-enetc-ierb"; 1162 reg = <0x01 0xf0800000 0x0 0x10000>; 1163 }; 1164 1165 rcpm: power-controller@1e34040 { 1166 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1167 reg = <0x0 0x1e34040 0x0 0x1c>; 1168 #fsl,rcpm-wakeup-cells = <7>; 1169 little-endian; 1170 }; 1171 1172 ftm_alarm0: timer@2800000 { 1173 compatible = "fsl,ls1028a-ftm-alarm"; 1174 reg = <0x0 0x2800000 0x0 0x10000>; 1175 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1176 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1177 }; 1178 }; 1179 1180}; 1181