1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3
4 #ifndef __HCLGEVF_CMD_H
5 #define __HCLGEVF_CMD_H
6 #include <linux/io.h>
7 #include <linux/types.h>
8 #include "hnae3.h"
9
10 #define HCLGEVF_CMDQ_TX_TIMEOUT 30000
11 #define HCLGEVF_CMDQ_CLEAR_WAIT_TIME 200
12 #define HCLGEVF_CMDQ_RX_INVLD_B 0
13 #define HCLGEVF_CMDQ_RX_OUTVLD_B 1
14
15 struct hclgevf_hw;
16 struct hclgevf_dev;
17
18 #define HCLGEVF_SYNC_RX_RING_HEAD_EN_B 4
19 struct hclgevf_firmware_compat_cmd {
20 __le32 compat;
21 u8 rsv[20];
22 };
23
24 struct hclgevf_desc {
25 __le16 opcode;
26 __le16 flag;
27 __le16 retval;
28 __le16 rsv;
29 __le32 data[6];
30 };
31
32 struct hclgevf_desc_cb {
33 dma_addr_t dma;
34 void *va;
35 u32 length;
36 };
37
38 struct hclgevf_cmq_ring {
39 dma_addr_t desc_dma_addr;
40 struct hclgevf_desc *desc;
41 struct hclgevf_desc_cb *desc_cb;
42 struct hclgevf_dev *dev;
43 u32 head;
44 u32 tail;
45
46 u16 buf_size;
47 u16 desc_num;
48 int next_to_use;
49 int next_to_clean;
50 u8 flag;
51 spinlock_t lock; /* Command queue lock */
52 };
53
54 enum hclgevf_cmd_return_status {
55 HCLGEVF_CMD_EXEC_SUCCESS = 0,
56 HCLGEVF_CMD_NO_AUTH = 1,
57 HCLGEVF_CMD_NOT_SUPPORTED = 2,
58 HCLGEVF_CMD_QUEUE_FULL = 3,
59 HCLGEVF_CMD_NEXT_ERR = 4,
60 HCLGEVF_CMD_UNEXE_ERR = 5,
61 HCLGEVF_CMD_PARA_ERR = 6,
62 HCLGEVF_CMD_RESULT_ERR = 7,
63 HCLGEVF_CMD_TIMEOUT = 8,
64 HCLGEVF_CMD_HILINK_ERR = 9,
65 HCLGEVF_CMD_QUEUE_ILLEGAL = 10,
66 HCLGEVF_CMD_INVALID = 11,
67 };
68
69 enum hclgevf_cmd_status {
70 HCLGEVF_STATUS_SUCCESS = 0,
71 HCLGEVF_ERR_CSQ_FULL = -1,
72 HCLGEVF_ERR_CSQ_TIMEOUT = -2,
73 HCLGEVF_ERR_CSQ_ERROR = -3
74 };
75
76 struct hclgevf_cmq {
77 struct hclgevf_cmq_ring csq;
78 struct hclgevf_cmq_ring crq;
79 u16 tx_timeout; /* Tx timeout */
80 enum hclgevf_cmd_status last_status;
81 };
82
83 #define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT 0
84 #define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT 1
85 #define HCLGEVF_CMD_FLAG_NEXT_SHIFT 2
86 #define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT 3
87 #define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT 4
88 #define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT 5
89
90 #define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT)
91 #define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT)
92 #define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT)
93 #define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT)
94 #define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT)
95 #define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT)
96
97 enum hclgevf_opcode_type {
98 /* Generic command */
99 HCLGEVF_OPC_QUERY_FW_VER = 0x0001,
100 HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024,
101 HCLGEVF_OPC_QUERY_DEV_SPECS = 0x0050,
102
103 /* TQP command */
104 HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
105 HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
106 HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
107 /* GRO command */
108 HCLGEVF_OPC_GRO_GENERIC_CONFIG = 0x0C10,
109 /* RSS cmd */
110 HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01,
111 HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02,
112 HCLGEVF_OPC_RSS_INDIR_TABLE = 0x0D07,
113 HCLGEVF_OPC_RSS_TC_MODE = 0x0D08,
114 /* Mailbox cmd */
115 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
116
117 /* IMP stats command */
118 HCLGEVF_OPC_IMP_COMPAT_CFG = 0x701A,
119 };
120
121 #define HCLGEVF_TQP_REG_OFFSET 0x80000
122 #define HCLGEVF_TQP_REG_SIZE 0x200
123
124 #define HCLGEVF_TQP_MAX_SIZE_DEV_V2 1024
125 #define HCLGEVF_TQP_EXT_REG_OFFSET 0x100
126
127 struct hclgevf_tqp_map {
128 __le16 tqp_id; /* Absolute tqp id for in this pf */
129 u8 tqp_vf; /* VF id */
130 #define HCLGEVF_TQP_MAP_TYPE_PF 0
131 #define HCLGEVF_TQP_MAP_TYPE_VF 1
132 #define HCLGEVF_TQP_MAP_TYPE_B 0
133 #define HCLGEVF_TQP_MAP_EN_B 1
134 u8 tqp_flag; /* Indicate it's pf or vf tqp */
135 __le16 tqp_vid; /* Virtual id in this pf/vf */
136 u8 rsv[18];
137 };
138
139 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10
140
141 enum hclgevf_int_type {
142 HCLGEVF_INT_TX = 0,
143 HCLGEVF_INT_RX,
144 HCLGEVF_INT_EVENT,
145 };
146
147 struct hclgevf_ctrl_vector_chain {
148 u8 int_vector_id;
149 u8 int_cause_num;
150 #define HCLGEVF_INT_TYPE_S 0
151 #define HCLGEVF_INT_TYPE_M 0x3
152 #define HCLGEVF_TQP_ID_S 2
153 #define HCLGEVF_TQP_ID_M (0x3fff << HCLGEVF_TQP_ID_S)
154 __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
155 u8 vfid;
156 u8 resv;
157 };
158
159 enum HCLGEVF_CAP_BITS {
160 HCLGEVF_CAP_UDP_GSO_B,
161 HCLGEVF_CAP_QB_B,
162 HCLGEVF_CAP_FD_FORWARD_TC_B,
163 HCLGEVF_CAP_PTP_B,
164 HCLGEVF_CAP_INT_QL_B,
165 HCLGEVF_CAP_HW_TX_CSUM_B,
166 HCLGEVF_CAP_TX_PUSH_B,
167 HCLGEVF_CAP_PHY_IMP_B,
168 HCLGEVF_CAP_TQP_TXRX_INDEP_B,
169 HCLGEVF_CAP_HW_PAD_B,
170 HCLGEVF_CAP_STASH_B,
171 HCLGEVF_CAP_UDP_TUNNEL_CSUM_B,
172 HCLGEVF_CAP_RXD_ADV_LAYOUT_B = 15,
173 };
174
175 enum HCLGEVF_API_CAP_BITS {
176 HCLGEVF_API_CAP_FLEX_RSS_TBL_B,
177 };
178
179 #define HCLGEVF_QUERY_CAP_LENGTH 3
180 struct hclgevf_query_version_cmd {
181 __le32 firmware;
182 __le32 hardware;
183 __le32 api_caps;
184 __le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
185 };
186
187 #define HCLGEVF_MSIX_OFT_ROCEE_S 0
188 #define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
189 #define HCLGEVF_VEC_NUM_S 0
190 #define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S)
191 struct hclgevf_query_res_cmd {
192 __le16 tqp_num;
193 __le16 reserved;
194 __le16 msixcap_localid_ba_nic;
195 __le16 msixcap_localid_ba_rocee;
196 __le16 vf_intr_vector_number;
197 __le16 rsv[7];
198 };
199
200 #define HCLGEVF_GRO_EN_B 0
201 struct hclgevf_cfg_gro_status_cmd {
202 u8 gro_en;
203 u8 rsv[23];
204 };
205
206 #define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4
207 #define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4
208 #define HCLGEVF_RSS_HASH_KEY_NUM 16
209 struct hclgevf_rss_config_cmd {
210 u8 hash_config;
211 u8 rsv[7];
212 u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM];
213 };
214
215 struct hclgevf_rss_input_tuple_cmd {
216 u8 ipv4_tcp_en;
217 u8 ipv4_udp_en;
218 u8 ipv4_sctp_en;
219 u8 ipv4_fragment_en;
220 u8 ipv6_tcp_en;
221 u8 ipv6_udp_en;
222 u8 ipv6_sctp_en;
223 u8 ipv6_fragment_en;
224 u8 rsv[16];
225 };
226
227 #define HCLGEVF_RSS_CFG_TBL_SIZE 16
228
229 struct hclgevf_rss_indirection_table_cmd {
230 __le16 start_table_index;
231 __le16 rss_set_bitmap;
232 u8 rsv[4];
233 u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE];
234 };
235
236 #define HCLGEVF_RSS_TC_OFFSET_S 0
237 #define HCLGEVF_RSS_TC_OFFSET_M GENMASK(10, 0)
238 #define HCLGEVF_RSS_TC_SIZE_MSB_B 11
239 #define HCLGEVF_RSS_TC_SIZE_S 12
240 #define HCLGEVF_RSS_TC_SIZE_M GENMASK(14, 12)
241 #define HCLGEVF_RSS_TC_VALID_B 15
242 #define HCLGEVF_MAX_TC_NUM 8
243 #define HCLGEVF_RSS_TC_SIZE_MSB_OFFSET 3
244
245 struct hclgevf_rss_tc_mode_cmd {
246 __le16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
247 u8 rsv[8];
248 };
249
250 #define HCLGEVF_LINK_STS_B 0
251 #define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B)
252 struct hclgevf_link_status_cmd {
253 u8 status;
254 u8 rsv[23];
255 };
256
257 #define HCLGEVF_RING_ID_MASK 0x3ff
258 #define HCLGEVF_TQP_ENABLE_B 0
259
260 struct hclgevf_cfg_com_tqp_queue_cmd {
261 __le16 tqp_id;
262 __le16 stream_id;
263 u8 enable;
264 u8 rsv[19];
265 };
266
267 struct hclgevf_cfg_tx_queue_pointer_cmd {
268 __le16 tqp_id;
269 __le16 tx_tail;
270 __le16 tx_head;
271 __le16 fbd_num;
272 __le16 ring_offset;
273 u8 rsv[14];
274 };
275
276 #define HCLGEVF_TYPE_CRQ 0
277 #define HCLGEVF_TYPE_CSQ 1
278
279 /* this bit indicates that the driver is ready for hardware reset */
280 #define HCLGEVF_NIC_SW_RST_RDY_B 16
281 #define HCLGEVF_NIC_SW_RST_RDY BIT(HCLGEVF_NIC_SW_RST_RDY_B)
282
283 #define HCLGEVF_NIC_CMQ_DESC_NUM 1024
284 #define HCLGEVF_NIC_CMQ_DESC_NUM_S 3
285
286 #define HCLGEVF_QUERY_DEV_SPECS_BD_NUM 4
287
288 struct hclgevf_dev_specs_0_cmd {
289 __le32 rsv0;
290 __le32 mac_entry_num;
291 __le32 mng_entry_num;
292 __le16 rss_ind_tbl_size;
293 __le16 rss_key_size;
294 __le16 int_ql_max;
295 u8 max_non_tso_bd_num;
296 u8 rsv1[5];
297 };
298
299 #define HCLGEVF_DEF_MAX_INT_GL 0x1FE0U
300
301 struct hclgevf_dev_specs_1_cmd {
302 __le16 max_frm_size;
303 __le16 rsv0;
304 __le16 max_int_gl;
305 u8 rsv1[18];
306 };
307
308 /* capabilities bits map between imp firmware and local driver */
309 struct hclgevf_caps_bit_map {
310 u16 imp_bit;
311 u16 local_bit;
312 };
313
hclgevf_write_reg(void __iomem * base,u32 reg,u32 value)314 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
315 {
316 writel(value, base + reg);
317 }
318
hclgevf_read_reg(u8 __iomem * base,u32 reg)319 static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
320 {
321 u8 __iomem *reg_addr = READ_ONCE(base);
322
323 return readl(reg_addr + reg);
324 }
325
326 #define hclgevf_write_dev(a, reg, value) \
327 hclgevf_write_reg((a)->io_base, reg, value)
328 #define hclgevf_read_dev(a, reg) \
329 hclgevf_read_reg((a)->io_base, reg)
330
331 #define HCLGEVF_SEND_SYNC(flag) \
332 ((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
333
334 int hclgevf_cmd_init(struct hclgevf_dev *hdev);
335 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
336 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
337
338 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
339 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
340 enum hclgevf_opcode_type opcode,
341 bool is_read);
342 #endif
343