1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
5 */
6/dts-v1/;
7
8#include "skeleton.dtsi"
9#include "dt-bindings/clock/snps,hsdk-cgu.h"
10#include "dt-bindings/reset/snps,hsdk-reset.h"
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	aliases {
17		console = &uart0;
18		spi0 = &spi0;
19	};
20
21	cpu_card {
22		core_clk: core_clk {
23			#clock-cells = <0>;
24			compatible = "fixed-clock";
25			clock-frequency = <500000000>;
26			u-boot,dm-pre-reloc;
27		};
28	};
29
30	clk-fmeas {
31		clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
32			 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
33			 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
34			 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
35			 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
36			 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
37			 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
38			 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
39			 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
40			 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
41			 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
42			 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
43			 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>,
44			 <&cgu_clk CLK_TUN_TIMER>;
45		clock-names = "cpu-pll", "sys-pll",
46			      "tun-pll", "ddr-clk",
47			      "cpu-clk", "hdmi-pll",
48			      "tun-clk", "hdmi-clk",
49			      "apb-clk", "axi-clk",
50			      "eth-clk", "usb-clk",
51			      "sdio-clk", "hdmi-sys-clk",
52			      "gfx-core-clk", "gfx-dma-clk",
53			      "gfx-cfg-clk", "dmac-core-clk",
54			      "dmac-cfg-clk", "sdio-ref-clk",
55			      "spi-clk", "i2c-clk",
56			      "uart-clk", "ebi-clk",
57			      "rom-clk", "pwm-clk",
58			      "timer-clk";
59	};
60
61	cgu_clk: cgu-clk@f0000000 {
62		compatible = "snps,hsdk-cgu-clock";
63		reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
64		#clock-cells = <1>;
65	};
66
67	cgu_rst: reset-controller@f00008a0 {
68		compatible = "snps,hsdk-reset";
69		#reset-cells = <1>;
70		reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
71	};
72
73	uart0: serial0@f0005000 {
74		compatible = "snps,dw-apb-uart";
75		reg = <0xf0005000 0x1000>;
76		reg-shift = <2>;
77		reg-io-width = <4>;
78	};
79
80	ethernet@f0008000 {
81		#interrupt-cells = <1>;
82		compatible = "snps,arc-dwmac-3.70a";
83		reg = <0xf0008000 0x2000>;
84		phy-mode = "gmii";
85	};
86
87	ehci@f0040000 {
88		compatible = "generic-ehci";
89		reg = <0xf0040000 0x100>;
90
91		/*
92		 * OHCI and EHCI have reset line shared so we don't add
93		 * reset property to OHCI node as it is probed later and
94		 * it will reset sucessfuly probed and configured EHCI HW.
95		 */
96		resets = <&cgu_rst HSDK_USB_RESET>;
97	};
98
99	ohci@f0060000 {
100		compatible = "generic-ohci";
101		reg = <0xf0060000 0x100>;
102	};
103
104	mmcclk_ciu: mmcclk-ciu {
105		compatible = "fixed-clock";
106		/*
107		 * DW sdio controller has external ciu clock divider
108		 * controlled via register in SDIO IP. Due to its
109		 * unexpected default value (it should divide by 1
110		 * but it divides by 8) SDIO IP uses wrong clock and
111		 * works unstable (see STAR 9001204800)
112		 * We switched to the minimum possible value of the
113		 * divisor (div-by-2) in HSDK platform code.
114		 * So default mmcclk ciu clock is 50000000 Hz.
115		 */
116		clock-frequency = <50000000>;
117		#clock-cells = <0>;
118	};
119
120	mmc: mmc0@f000a000 {
121		compatible = "snps,dw-mshc";
122		reg = <0xf000a000 0x400>;
123		bus-width = <4>;
124		fifo-depth = <256>;
125		clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
126		clock-names = "biu", "ciu";
127		max-frequency = <25000000>;
128	};
129
130	spi0: spi@f0020000 {
131		compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
132		reg = <0xf0020000 0x1000>;
133		#address-cells = <1>;
134		#size-cells = <0>;
135		spi-max-frequency = <4000000>;
136		clocks = <&cgu_clk CLK_SYS_SPI_REF>;
137		clock-names = "spi_clk";
138		num-cs = <1>;
139		cs-gpios = <&cs_gpio 0>;
140		spi_flash@0 {
141			compatible = "jedec,spi-nor";
142			reg = <0>;
143			spi-max-frequency = <4000000>;
144		};
145	};
146
147	cs_gpio: gpio@f00014b0 {
148		compatible = "snps,creg-gpio";
149		reg = <0xf00014b0 0x4>;
150		gpio-controller;
151		#gpio-cells = <1>;
152		gpio-bank-name = "hsdk-spi-cs";
153		gpio-count = <1>;
154		gpio-first-shift = <0>;
155		gpio-bit-per-line = <2>;
156		gpio-activate-val = <2>;
157		gpio-deactivate-val = <3>;
158		gpio-default-val = <1>;
159	};
160};
161