1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/imx8mm-power.h> 11#include <dt-bindings/reset/imx8mq-reset.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mm-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; /* two CLK32 periods */ 66 clocks = <&clk IMX8MM_CLK_ARM>; 67 enable-method = "psci"; 68 next-level-cache = <&A53_L2>; 69 operating-points-v2 = <&a53_opp_table>; 70 nvmem-cells = <&cpu_speed_grade>; 71 nvmem-cell-names = "speed_grade"; 72 cpu-idle-states = <&cpu_pd_wait>; 73 #cooling-cells = <2>; 74 }; 75 76 A53_1: cpu@1 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x1>; 80 clock-latency = <61036>; /* two CLK32 periods */ 81 clocks = <&clk IMX8MM_CLK_ARM>; 82 enable-method = "psci"; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 cpu-idle-states = <&cpu_pd_wait>; 86 #cooling-cells = <2>; 87 }; 88 89 A53_2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x2>; 93 clock-latency = <61036>; /* two CLK32 periods */ 94 clocks = <&clk IMX8MM_CLK_ARM>; 95 enable-method = "psci"; 96 next-level-cache = <&A53_L2>; 97 operating-points-v2 = <&a53_opp_table>; 98 cpu-idle-states = <&cpu_pd_wait>; 99 #cooling-cells = <2>; 100 }; 101 102 A53_3: cpu@3 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53"; 105 reg = <0x3>; 106 clock-latency = <61036>; /* two CLK32 periods */ 107 clocks = <&clk IMX8MM_CLK_ARM>; 108 enable-method = "psci"; 109 next-level-cache = <&A53_L2>; 110 operating-points-v2 = <&a53_opp_table>; 111 cpu-idle-states = <&cpu_pd_wait>; 112 #cooling-cells = <2>; 113 }; 114 115 A53_L2: l2-cache0 { 116 compatible = "cache"; 117 }; 118 }; 119 120 a53_opp_table: opp-table { 121 compatible = "operating-points-v2"; 122 opp-shared; 123 124 opp-1200000000 { 125 opp-hz = /bits/ 64 <1200000000>; 126 opp-microvolt = <850000>; 127 opp-supported-hw = <0xe>, <0x7>; 128 clock-latency-ns = <150000>; 129 opp-suspend; 130 }; 131 132 opp-1600000000 { 133 opp-hz = /bits/ 64 <1600000000>; 134 opp-microvolt = <950000>; 135 opp-supported-hw = <0xc>, <0x7>; 136 clock-latency-ns = <150000>; 137 opp-suspend; 138 }; 139 140 opp-1800000000 { 141 opp-hz = /bits/ 64 <1800000000>; 142 opp-microvolt = <1000000>; 143 opp-supported-hw = <0x8>, <0x3>; 144 clock-latency-ns = <150000>; 145 opp-suspend; 146 }; 147 }; 148 149 osc_32k: clock-osc-32k { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <32768>; 153 clock-output-names = "osc_32k"; 154 }; 155 156 osc_24m: clock-osc-24m { 157 compatible = "fixed-clock"; 158 #clock-cells = <0>; 159 clock-frequency = <24000000>; 160 clock-output-names = "osc_24m"; 161 }; 162 163 clk_ext1: clock-ext1 { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <133000000>; 167 clock-output-names = "clk_ext1"; 168 }; 169 170 clk_ext2: clock-ext2 { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <133000000>; 174 clock-output-names = "clk_ext2"; 175 }; 176 177 clk_ext3: clock-ext3 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext3"; 182 }; 183 184 clk_ext4: clock-ext4 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency= <133000000>; 188 clock-output-names = "clk_ext4"; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 pmu { 197 compatible = "arm,cortex-a53-pmu"; 198 interrupts = <GIC_PPI 7 199 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 200 }; 201 202 timer { 203 compatible = "arm,armv8-timer"; 204 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 205 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 206 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 207 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 208 clock-frequency = <8000000>; 209 arm,no-tick-in-suspend; 210 }; 211 212 thermal-zones { 213 cpu-thermal { 214 polling-delay-passive = <250>; 215 polling-delay = <2000>; 216 thermal-sensors = <&tmu>; 217 trips { 218 cpu_alert0: trip0 { 219 temperature = <85000>; 220 hysteresis = <2000>; 221 type = "passive"; 222 }; 223 224 cpu_crit0: trip1 { 225 temperature = <95000>; 226 hysteresis = <2000>; 227 type = "critical"; 228 }; 229 }; 230 231 cooling-maps { 232 map0 { 233 trip = <&cpu_alert0>; 234 cooling-device = 235 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 236 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 237 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 238 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 239 }; 240 }; 241 }; 242 }; 243 244 usbphynop1: usbphynop1 { 245 #phy-cells = <0>; 246 compatible = "usb-nop-xceiv"; 247 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 248 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 249 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 250 clock-names = "main_clk"; 251 }; 252 253 usbphynop2: usbphynop2 { 254 #phy-cells = <0>; 255 compatible = "usb-nop-xceiv"; 256 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 257 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 258 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 259 clock-names = "main_clk"; 260 }; 261 262 soc@0 { 263 compatible = "fsl,imx8mm-soc", "simple-bus"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges = <0x0 0x0 0x0 0x3e000000>; 267 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 268 nvmem-cells = <&imx8mm_uid>; 269 nvmem-cell-names = "soc_unique_id"; 270 271 aips1: bus@30000000 { 272 compatible = "fsl,aips-bus", "simple-bus"; 273 reg = <0x30000000 0x400000>; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 ranges = <0x30000000 0x30000000 0x400000>; 277 278 spba2: spba-bus@30000000 { 279 compatible = "fsl,spba-bus", "simple-bus"; 280 #address-cells = <1>; 281 #size-cells = <1>; 282 reg = <0x30000000 0x100000>; 283 ranges; 284 285 sai1: sai@30010000 { 286 #sound-dai-cells = <0>; 287 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 288 reg = <0x30010000 0x10000>; 289 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 291 <&clk IMX8MM_CLK_SAI1_ROOT>, 292 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 293 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 294 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 295 dma-names = "rx", "tx"; 296 status = "disabled"; 297 }; 298 299 sai2: sai@30020000 { 300 #sound-dai-cells = <0>; 301 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 302 reg = <0x30020000 0x10000>; 303 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 305 <&clk IMX8MM_CLK_SAI2_ROOT>, 306 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 307 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 308 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 309 dma-names = "rx", "tx"; 310 status = "disabled"; 311 }; 312 313 sai3: sai@30030000 { 314 #sound-dai-cells = <0>; 315 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 316 reg = <0x30030000 0x10000>; 317 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 319 <&clk IMX8MM_CLK_SAI3_ROOT>, 320 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 321 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 322 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 323 dma-names = "rx", "tx"; 324 status = "disabled"; 325 }; 326 327 sai5: sai@30050000 { 328 #sound-dai-cells = <0>; 329 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 330 reg = <0x30050000 0x10000>; 331 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 333 <&clk IMX8MM_CLK_SAI5_ROOT>, 334 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 335 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 336 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 sai6: sai@30060000 { 342 #sound-dai-cells = <0>; 343 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 344 reg = <0x30060000 0x10000>; 345 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 347 <&clk IMX8MM_CLK_SAI6_ROOT>, 348 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 349 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 350 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 351 dma-names = "rx", "tx"; 352 status = "disabled"; 353 }; 354 355 micfil: audio-controller@30080000 { 356 compatible = "fsl,imx8mm-micfil"; 357 reg = <0x30080000 0x10000>; 358 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 363 <&clk IMX8MM_CLK_PDM_ROOT>, 364 <&clk IMX8MM_AUDIO_PLL1_OUT>, 365 <&clk IMX8MM_AUDIO_PLL2_OUT>, 366 <&clk IMX8MM_CLK_EXT3>; 367 clock-names = "ipg_clk", "ipg_clk_app", 368 "pll8k", "pll11k", "clkext3"; 369 dmas = <&sdma2 24 25 0x80000000>; 370 dma-names = "rx"; 371 status = "disabled"; 372 }; 373 374 spdif1: spdif@30090000 { 375 compatible = "fsl,imx35-spdif"; 376 reg = <0x30090000 0x10000>; 377 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 379 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 380 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 381 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 382 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 383 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 384 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 385 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 386 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 387 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 388 clock-names = "core", "rxtx0", 389 "rxtx1", "rxtx2", 390 "rxtx3", "rxtx4", 391 "rxtx5", "rxtx6", 392 "rxtx7", "spba"; 393 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 394 dma-names = "rx", "tx"; 395 status = "disabled"; 396 }; 397 }; 398 399 gpio1: gpio@30200000 { 400 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 401 reg = <0x30200000 0x10000>; 402 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 405 gpio-controller; 406 #gpio-cells = <2>; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 gpio-ranges = <&iomuxc 0 10 30>; 410 }; 411 412 gpio2: gpio@30210000 { 413 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 414 reg = <0x30210000 0x10000>; 415 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 418 gpio-controller; 419 #gpio-cells = <2>; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 gpio-ranges = <&iomuxc 0 40 21>; 423 }; 424 425 gpio3: gpio@30220000 { 426 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 427 reg = <0x30220000 0x10000>; 428 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 431 gpio-controller; 432 #gpio-cells = <2>; 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 gpio-ranges = <&iomuxc 0 61 26>; 436 }; 437 438 gpio4: gpio@30230000 { 439 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 440 reg = <0x30230000 0x10000>; 441 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 444 gpio-controller; 445 #gpio-cells = <2>; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 gpio-ranges = <&iomuxc 0 87 32>; 449 }; 450 451 gpio5: gpio@30240000 { 452 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 453 reg = <0x30240000 0x10000>; 454 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 gpio-ranges = <&iomuxc 0 119 30>; 462 }; 463 464 tmu: tmu@30260000 { 465 compatible = "fsl,imx8mm-tmu"; 466 reg = <0x30260000 0x10000>; 467 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 468 #thermal-sensor-cells = <0>; 469 }; 470 471 wdog1: watchdog@30280000 { 472 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 473 reg = <0x30280000 0x10000>; 474 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 476 status = "disabled"; 477 }; 478 479 wdog2: watchdog@30290000 { 480 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 481 reg = <0x30290000 0x10000>; 482 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 484 status = "disabled"; 485 }; 486 487 wdog3: watchdog@302a0000 { 488 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 489 reg = <0x302a0000 0x10000>; 490 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 492 status = "disabled"; 493 }; 494 495 sdma2: dma-controller@302c0000 { 496 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 497 reg = <0x302c0000 0x10000>; 498 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 500 <&clk IMX8MM_CLK_SDMA2_ROOT>; 501 clock-names = "ipg", "ahb"; 502 #dma-cells = <3>; 503 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 504 }; 505 506 sdma3: dma-controller@302b0000 { 507 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 508 reg = <0x302b0000 0x10000>; 509 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 511 <&clk IMX8MM_CLK_SDMA3_ROOT>; 512 clock-names = "ipg", "ahb"; 513 #dma-cells = <3>; 514 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 515 }; 516 517 iomuxc: pinctrl@30330000 { 518 compatible = "fsl,imx8mm-iomuxc"; 519 reg = <0x30330000 0x10000>; 520 }; 521 522 gpr: iomuxc-gpr@30340000 { 523 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 524 reg = <0x30340000 0x10000>; 525 }; 526 527 ocotp: efuse@30350000 { 528 compatible = "fsl,imx8mm-ocotp", "syscon"; 529 reg = <0x30350000 0x10000>; 530 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 531 /* For nvmem subnodes */ 532 #address-cells = <1>; 533 #size-cells = <1>; 534 535 imx8mm_uid: unique-id@410 { 536 reg = <0x4 0x8>; 537 }; 538 539 cpu_speed_grade: speed-grade@10 { 540 reg = <0x10 4>; 541 }; 542 543 fec_mac_address: mac-address@90 { 544 reg = <0x90 6>; 545 }; 546 }; 547 548 anatop: anatop@30360000 { 549 compatible = "fsl,imx8mm-anatop", "syscon"; 550 reg = <0x30360000 0x10000>; 551 }; 552 553 snvs: snvs@30370000 { 554 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 555 reg = <0x30370000 0x10000>; 556 557 snvs_rtc: snvs-rtc-lp { 558 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 559 regmap = <&snvs>; 560 offset = <0x34>; 561 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 564 clock-names = "snvs-rtc"; 565 }; 566 567 snvs_pwrkey: snvs-powerkey { 568 compatible = "fsl,sec-v4.0-pwrkey"; 569 regmap = <&snvs>; 570 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 572 clock-names = "snvs-pwrkey"; 573 linux,keycode = <KEY_POWER>; 574 wakeup-source; 575 status = "disabled"; 576 }; 577 }; 578 579 clk: clock-controller@30380000 { 580 compatible = "fsl,imx8mm-ccm"; 581 reg = <0x30380000 0x10000>; 582 #clock-cells = <1>; 583 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 584 <&clk_ext3>, <&clk_ext4>; 585 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 586 "clk_ext3", "clk_ext4"; 587 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 588 <&clk IMX8MM_CLK_A53_CORE>, 589 <&clk IMX8MM_CLK_NOC>, 590 <&clk IMX8MM_CLK_AUDIO_AHB>, 591 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 592 <&clk IMX8MM_SYS_PLL3>, 593 <&clk IMX8MM_VIDEO_PLL1>, 594 <&clk IMX8MM_AUDIO_PLL1>, 595 <&clk IMX8MM_AUDIO_PLL2>; 596 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 597 <&clk IMX8MM_ARM_PLL_OUT>, 598 <&clk IMX8MM_SYS_PLL3_OUT>, 599 <&clk IMX8MM_SYS_PLL1_800M>; 600 assigned-clock-rates = <0>, <0>, <0>, 601 <400000000>, 602 <400000000>, 603 <750000000>, 604 <594000000>, 605 <393216000>, 606 <361267200>; 607 }; 608 609 src: reset-controller@30390000 { 610 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 611 reg = <0x30390000 0x10000>; 612 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 613 #reset-cells = <1>; 614 }; 615 616 gpc: gpc@303a0000 { 617 compatible = "fsl,imx8mm-gpc"; 618 reg = <0x303a0000 0x10000>; 619 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 620 interrupt-parent = <&gic>; 621 interrupt-controller; 622 #interrupt-cells = <3>; 623 624 pgc { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 628 pgc_hsiomix: power-domain@0 { 629 #power-domain-cells = <0>; 630 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; 631 clocks = <&clk IMX8MM_CLK_USB_BUS>; 632 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 633 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 634 }; 635 636 pgc_pcie: power-domain@1 { 637 #power-domain-cells = <0>; 638 reg = <IMX8MM_POWER_DOMAIN_PCIE>; 639 power-domains = <&pgc_hsiomix>; 640 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; 641 }; 642 643 pgc_otg1: power-domain@2 { 644 #power-domain-cells = <0>; 645 reg = <IMX8MM_POWER_DOMAIN_OTG1>; 646 power-domains = <&pgc_hsiomix>; 647 }; 648 649 pgc_otg2: power-domain@3 { 650 #power-domain-cells = <0>; 651 reg = <IMX8MM_POWER_DOMAIN_OTG2>; 652 power-domains = <&pgc_hsiomix>; 653 }; 654 655 pgc_gpumix: power-domain@4 { 656 #power-domain-cells = <0>; 657 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; 658 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 659 <&clk IMX8MM_CLK_GPU_AHB>; 660 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>, 661 <&clk IMX8MM_CLK_GPU_AHB>; 662 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 663 <&clk IMX8MM_SYS_PLL1_800M>; 664 assigned-clock-rates = <800000000>, <400000000>; 665 }; 666 667 pgc_gpu: power-domain@5 { 668 #power-domain-cells = <0>; 669 reg = <IMX8MM_POWER_DOMAIN_GPU>; 670 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 671 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 672 <&clk IMX8MM_CLK_GPU2D_ROOT>, 673 <&clk IMX8MM_CLK_GPU3D_ROOT>; 674 resets = <&src IMX8MQ_RESET_GPU_RESET>; 675 power-domains = <&pgc_gpumix>; 676 }; 677 678 pgc_vpumix: power-domain@6 { 679 #power-domain-cells = <0>; 680 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>; 681 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; 682 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; 683 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; 684 resets = <&src IMX8MQ_RESET_VPU_RESET>; 685 }; 686 687 pgc_vpu_g1: power-domain@7 { 688 #power-domain-cells = <0>; 689 reg = <IMX8MM_POWER_DOMAIN_VPUG1>; 690 }; 691 692 pgc_vpu_g2: power-domain@8 { 693 #power-domain-cells = <0>; 694 reg = <IMX8MM_POWER_DOMAIN_VPUG2>; 695 }; 696 697 pgc_vpu_h1: power-domain@9 { 698 #power-domain-cells = <0>; 699 reg = <IMX8MM_POWER_DOMAIN_VPUH1>; 700 }; 701 702 pgc_dispmix: power-domain@10 { 703 #power-domain-cells = <0>; 704 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>; 705 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 706 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 707 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>, 708 <&clk IMX8MM_CLK_DISP_APB>; 709 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 710 <&clk IMX8MM_SYS_PLL1_800M>; 711 assigned-clock-rates = <500000000>, <200000000>; 712 }; 713 714 pgc_mipi: power-domain@11 { 715 #power-domain-cells = <0>; 716 reg = <IMX8MM_POWER_DOMAIN_MIPI>; 717 }; 718 }; 719 }; 720 }; 721 722 aips2: bus@30400000 { 723 compatible = "fsl,aips-bus", "simple-bus"; 724 reg = <0x30400000 0x400000>; 725 #address-cells = <1>; 726 #size-cells = <1>; 727 ranges = <0x30400000 0x30400000 0x400000>; 728 729 pwm1: pwm@30660000 { 730 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 731 reg = <0x30660000 0x10000>; 732 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 734 <&clk IMX8MM_CLK_PWM1_ROOT>; 735 clock-names = "ipg", "per"; 736 #pwm-cells = <2>; 737 status = "disabled"; 738 }; 739 740 pwm2: pwm@30670000 { 741 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 742 reg = <0x30670000 0x10000>; 743 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 745 <&clk IMX8MM_CLK_PWM2_ROOT>; 746 clock-names = "ipg", "per"; 747 #pwm-cells = <2>; 748 status = "disabled"; 749 }; 750 751 pwm3: pwm@30680000 { 752 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 753 reg = <0x30680000 0x10000>; 754 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 756 <&clk IMX8MM_CLK_PWM3_ROOT>; 757 clock-names = "ipg", "per"; 758 #pwm-cells = <2>; 759 status = "disabled"; 760 }; 761 762 pwm4: pwm@30690000 { 763 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 764 reg = <0x30690000 0x10000>; 765 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 767 <&clk IMX8MM_CLK_PWM4_ROOT>; 768 clock-names = "ipg", "per"; 769 #pwm-cells = <2>; 770 status = "disabled"; 771 }; 772 773 system_counter: timer@306a0000 { 774 compatible = "nxp,sysctr-timer"; 775 reg = <0x306a0000 0x20000>; 776 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&osc_24m>; 778 clock-names = "per"; 779 }; 780 }; 781 782 aips3: bus@30800000 { 783 compatible = "fsl,aips-bus", "simple-bus"; 784 reg = <0x30800000 0x400000>; 785 #address-cells = <1>; 786 #size-cells = <1>; 787 ranges = <0x30800000 0x30800000 0x400000>, 788 <0x8000000 0x8000000 0x10000000>; 789 790 spba1: spba-bus@30800000 { 791 compatible = "fsl,spba-bus", "simple-bus"; 792 #address-cells = <1>; 793 #size-cells = <1>; 794 reg = <0x30800000 0x100000>; 795 ranges; 796 797 ecspi1: spi@30820000 { 798 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 reg = <0x30820000 0x10000>; 802 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 804 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 805 clock-names = "ipg", "per"; 806 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 807 dma-names = "rx", "tx"; 808 status = "disabled"; 809 }; 810 811 ecspi2: spi@30830000 { 812 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 reg = <0x30830000 0x10000>; 816 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 818 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 819 clock-names = "ipg", "per"; 820 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 821 dma-names = "rx", "tx"; 822 status = "disabled"; 823 }; 824 825 ecspi3: spi@30840000 { 826 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 reg = <0x30840000 0x10000>; 830 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 832 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 833 clock-names = "ipg", "per"; 834 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 835 dma-names = "rx", "tx"; 836 status = "disabled"; 837 }; 838 839 uart1: serial@30860000 { 840 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 841 reg = <0x30860000 0x10000>; 842 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 844 <&clk IMX8MM_CLK_UART1_ROOT>; 845 clock-names = "ipg", "per"; 846 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 847 dma-names = "rx", "tx"; 848 status = "disabled"; 849 }; 850 851 uart3: serial@30880000 { 852 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 853 reg = <0x30880000 0x10000>; 854 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 856 <&clk IMX8MM_CLK_UART3_ROOT>; 857 clock-names = "ipg", "per"; 858 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 859 dma-names = "rx", "tx"; 860 status = "disabled"; 861 }; 862 863 uart2: serial@30890000 { 864 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 865 reg = <0x30890000 0x10000>; 866 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 868 <&clk IMX8MM_CLK_UART2_ROOT>; 869 clock-names = "ipg", "per"; 870 status = "disabled"; 871 }; 872 }; 873 874 crypto: crypto@30900000 { 875 compatible = "fsl,sec-v4.0"; 876 #address-cells = <1>; 877 #size-cells = <1>; 878 reg = <0x30900000 0x40000>; 879 ranges = <0 0x30900000 0x40000>; 880 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&clk IMX8MM_CLK_AHB>, 882 <&clk IMX8MM_CLK_IPG_ROOT>; 883 clock-names = "aclk", "ipg"; 884 885 sec_jr0: jr@1000 { 886 compatible = "fsl,sec-v4.0-job-ring"; 887 reg = <0x1000 0x1000>; 888 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 889 }; 890 891 sec_jr1: jr@2000 { 892 compatible = "fsl,sec-v4.0-job-ring"; 893 reg = <0x2000 0x1000>; 894 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 895 }; 896 897 sec_jr2: jr@3000 { 898 compatible = "fsl,sec-v4.0-job-ring"; 899 reg = <0x3000 0x1000>; 900 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 901 }; 902 }; 903 904 i2c1: i2c@30a20000 { 905 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 reg = <0x30a20000 0x10000>; 909 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 911 status = "disabled"; 912 }; 913 914 i2c2: i2c@30a30000 { 915 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 reg = <0x30a30000 0x10000>; 919 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 921 status = "disabled"; 922 }; 923 924 i2c3: i2c@30a40000 { 925 #address-cells = <1>; 926 #size-cells = <0>; 927 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 928 reg = <0x30a40000 0x10000>; 929 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 931 status = "disabled"; 932 }; 933 934 i2c4: i2c@30a50000 { 935 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 reg = <0x30a50000 0x10000>; 939 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 941 status = "disabled"; 942 }; 943 944 uart4: serial@30a60000 { 945 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 946 reg = <0x30a60000 0x10000>; 947 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 949 <&clk IMX8MM_CLK_UART4_ROOT>; 950 clock-names = "ipg", "per"; 951 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 952 dma-names = "rx", "tx"; 953 status = "disabled"; 954 }; 955 956 mu: mailbox@30aa0000 { 957 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 958 reg = <0x30aa0000 0x10000>; 959 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 961 #mbox-cells = <2>; 962 }; 963 964 usdhc1: mmc@30b40000 { 965 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 966 reg = <0x30b40000 0x10000>; 967 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 969 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 970 <&clk IMX8MM_CLK_USDHC1_ROOT>; 971 clock-names = "ipg", "ahb", "per"; 972 fsl,tuning-start-tap = <20>; 973 fsl,tuning-step= <2>; 974 bus-width = <4>; 975 status = "disabled"; 976 }; 977 978 usdhc2: mmc@30b50000 { 979 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 980 reg = <0x30b50000 0x10000>; 981 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 983 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 984 <&clk IMX8MM_CLK_USDHC2_ROOT>; 985 clock-names = "ipg", "ahb", "per"; 986 fsl,tuning-start-tap = <20>; 987 fsl,tuning-step= <2>; 988 bus-width = <4>; 989 status = "disabled"; 990 }; 991 992 usdhc3: mmc@30b60000 { 993 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 994 reg = <0x30b60000 0x10000>; 995 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 997 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 998 <&clk IMX8MM_CLK_USDHC3_ROOT>; 999 clock-names = "ipg", "ahb", "per"; 1000 fsl,tuning-start-tap = <20>; 1001 fsl,tuning-step= <2>; 1002 bus-width = <4>; 1003 status = "disabled"; 1004 }; 1005 1006 flexspi: spi@30bb0000 { 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 compatible = "nxp,imx8mm-fspi"; 1010 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1011 reg-names = "fspi_base", "fspi_mmap"; 1012 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 1014 <&clk IMX8MM_CLK_QSPI_ROOT>; 1015 clock-names = "fspi_en", "fspi"; 1016 status = "disabled"; 1017 }; 1018 1019 sdma1: dma-controller@30bd0000 { 1020 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 1021 reg = <0x30bd0000 0x10000>; 1022 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 1024 <&clk IMX8MM_CLK_AHB>; 1025 clock-names = "ipg", "ahb"; 1026 #dma-cells = <3>; 1027 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1028 }; 1029 1030 fec1: ethernet@30be0000 { 1031 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1032 reg = <0x30be0000 0x10000>; 1033 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 1038 <&clk IMX8MM_CLK_ENET1_ROOT>, 1039 <&clk IMX8MM_CLK_ENET_TIMER>, 1040 <&clk IMX8MM_CLK_ENET_REF>, 1041 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1042 clock-names = "ipg", "ahb", "ptp", 1043 "enet_clk_ref", "enet_out"; 1044 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 1045 <&clk IMX8MM_CLK_ENET_TIMER>, 1046 <&clk IMX8MM_CLK_ENET_REF>, 1047 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1048 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 1049 <&clk IMX8MM_SYS_PLL2_100M>, 1050 <&clk IMX8MM_SYS_PLL2_125M>, 1051 <&clk IMX8MM_SYS_PLL2_50M>; 1052 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1053 fsl,num-tx-queues = <3>; 1054 fsl,num-rx-queues = <3>; 1055 nvmem-cells = <&fec_mac_address>; 1056 nvmem-cell-names = "mac-address"; 1057 nvmem_macaddr_swap; 1058 fsl,stop-mode = <&gpr 0x10 3>; 1059 status = "disabled"; 1060 }; 1061 1062 }; 1063 1064 aips4: bus@32c00000 { 1065 compatible = "fsl,aips-bus", "simple-bus"; 1066 reg = <0x32c00000 0x400000>; 1067 #address-cells = <1>; 1068 #size-cells = <1>; 1069 ranges = <0x32c00000 0x32c00000 0x400000>; 1070 1071 disp_blk_ctrl: blk-ctrl@32e28000 { 1072 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; 1073 reg = <0x32e28000 0x100>; 1074 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1075 <&pgc_dispmix>, <&pgc_mipi>, 1076 <&pgc_mipi>; 1077 power-domain-names = "bus", "csi-bridge", 1078 "lcdif", "mipi-dsi", 1079 "mipi-csi"; 1080 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1081 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1082 <&clk IMX8MM_CLK_CSI1_ROOT>, 1083 <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1084 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1085 <&clk IMX8MM_CLK_DISP_ROOT>, 1086 <&clk IMX8MM_CLK_DSI_CORE>, 1087 <&clk IMX8MM_CLK_DSI_PHY_REF>, 1088 <&clk IMX8MM_CLK_CSI1_CORE>, 1089 <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1090 clock-names = "csi-bridge-axi","csi-bridge-apb", 1091 "csi-bridge-core", "lcdif-axi", 1092 "lcdif-apb", "lcdif-pix", 1093 "dsi-pclk", "dsi-ref", 1094 "csi-aclk", "csi-pclk"; 1095 #power-domain-cells = <1>; 1096 }; 1097 1098 usbotg1: usb@32e40000 { 1099 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1100 reg = <0x32e40000 0x200>; 1101 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1103 clock-names = "usb1_ctrl_root_clk"; 1104 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1105 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1106 phys = <&usbphynop1>; 1107 fsl,usbmisc = <&usbmisc1 0>; 1108 power-domains = <&pgc_otg1>; 1109 status = "disabled"; 1110 }; 1111 1112 usbmisc1: usbmisc@32e40200 { 1113 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1114 #index-cells = <1>; 1115 reg = <0x32e40200 0x200>; 1116 }; 1117 1118 usbotg2: usb@32e50000 { 1119 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1120 reg = <0x32e50000 0x200>; 1121 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1123 clock-names = "usb1_ctrl_root_clk"; 1124 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1125 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1126 phys = <&usbphynop2>; 1127 fsl,usbmisc = <&usbmisc2 0>; 1128 power-domains = <&pgc_otg2>; 1129 status = "disabled"; 1130 }; 1131 1132 usbmisc2: usbmisc@32e50200 { 1133 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1134 #index-cells = <1>; 1135 reg = <0x32e50200 0x200>; 1136 }; 1137 1138 }; 1139 1140 dma_apbh: dma-controller@33000000 { 1141 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1142 reg = <0x33000000 0x2000>; 1143 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1147 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1148 #dma-cells = <1>; 1149 dma-channels = <4>; 1150 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1151 }; 1152 1153 gpmi: nand-controller@33002000{ 1154 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1155 #address-cells = <1>; 1156 #size-cells = <1>; 1157 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1158 reg-names = "gpmi-nand", "bch"; 1159 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1160 interrupt-names = "bch"; 1161 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1162 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1163 clock-names = "gpmi_io", "gpmi_bch_apb"; 1164 dmas = <&dma_apbh 0>; 1165 dma-names = "rx-tx"; 1166 status = "disabled"; 1167 }; 1168 1169 gpu_3d: gpu@38000000 { 1170 compatible = "vivante,gc"; 1171 reg = <0x38000000 0x8000>; 1172 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1174 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1175 <&clk IMX8MM_CLK_GPU3D_ROOT>, 1176 <&clk IMX8MM_CLK_GPU3D_ROOT>; 1177 clock-names = "reg", "bus", "core", "shader"; 1178 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, 1179 <&clk IMX8MM_GPU_PLL_OUT>; 1180 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1181 assigned-clock-rates = <0>, <1000000000>; 1182 power-domains = <&pgc_gpu>; 1183 }; 1184 1185 gpu_2d: gpu@38008000 { 1186 compatible = "vivante,gc"; 1187 reg = <0x38008000 0x8000>; 1188 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1190 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1191 <&clk IMX8MM_CLK_GPU2D_ROOT>; 1192 clock-names = "reg", "bus", "core"; 1193 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, 1194 <&clk IMX8MM_GPU_PLL_OUT>; 1195 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1196 assigned-clock-rates = <0>, <1000000000>; 1197 power-domains = <&pgc_gpu>; 1198 }; 1199 1200 vpu_blk_ctrl: blk-ctrl@38330000 { 1201 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; 1202 reg = <0x38330000 0x100>; 1203 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1204 <&pgc_vpu_g2>, <&pgc_vpu_h1>; 1205 power-domain-names = "bus", "g1", "g2", "h1"; 1206 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, 1207 <&clk IMX8MM_CLK_VPU_G2_ROOT>, 1208 <&clk IMX8MM_CLK_VPU_H1_ROOT>; 1209 clock-names = "g1", "g2", "h1"; 1210 #power-domain-cells = <1>; 1211 }; 1212 1213 gic: interrupt-controller@38800000 { 1214 compatible = "arm,gic-v3"; 1215 reg = <0x38800000 0x10000>, /* GIC Dist */ 1216 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1217 #interrupt-cells = <3>; 1218 interrupt-controller; 1219 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1220 }; 1221 1222 ddrc: memory-controller@3d400000 { 1223 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1224 reg = <0x3d400000 0x400000>; 1225 clock-names = "core", "pll", "alt", "apb"; 1226 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1227 <&clk IMX8MM_DRAM_PLL>, 1228 <&clk IMX8MM_CLK_DRAM_ALT>, 1229 <&clk IMX8MM_CLK_DRAM_APB>; 1230 }; 1231 1232 ddr-pmu@3d800000 { 1233 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1234 reg = <0x3d800000 0x400000>; 1235 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1236 }; 1237 }; 1238}; 1239