1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Common configuration settings for IGEP technology based boards 4 * 5 * (C) Copyright 2012 6 * ISEE 2007 SL, <www.iseebcn.com> 7 */ 8 9 #ifndef __IGEP00X0_H 10 #define __IGEP00X0_H 11 12 #include <configs/ti_omap3_common.h> 13 14 /* 15 * We are only ever GP parts and will utilize all of the "downloaded image" 16 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). 17 */ 18 19 #define CONFIG_REVISION_TAG 1 20 21 /* TPS65950 */ 22 #define PBIASLITEVMODE1 (1 << 8) 23 24 /* LED */ 25 #define IGEP0020_GPIO_LED 27 26 #define IGEP0030_GPIO_LED 16 27 28 /* Board and revision detection GPIOs */ 29 #define IGEP0030_USB_TRANSCEIVER_RESET 54 30 #define GPIO_IGEP00X0_BOARD_DETECTION 28 31 #define GPIO_IGEP00X0_REVISION_DETECTION 129 32 33 #ifndef CONFIG_SPL_BUILD 34 35 /* Environment */ 36 #define ENV_DEVICE_SETTINGS \ 37 "stdin=serial\0" \ 38 "stdout=serial\0" \ 39 "stderr=serial\0" 40 41 #define MEM_LAYOUT_SETTINGS \ 42 DEFAULT_LINUX_BOOT_ENV \ 43 "scriptaddr=0x87E00000\0" \ 44 "pxefile_addr_r=0x87F00000\0" 45 46 #define BOOT_TARGET_DEVICES(func) \ 47 func(MMC, mmc, 0) 48 49 #include <config_distro_bootcmd.h> 50 51 #define ENV_FINDFDT \ 52 "findfdt="\ 53 "if test ${board_name} = igep0020; then " \ 54 "if test ${board_rev} = F; then " \ 55 "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ 56 "else " \ 57 "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ 58 "if test ${board_name} = igep0030; then " \ 59 "if test ${board_rev} = G; then " \ 60 "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ 61 "else " \ 62 "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ 63 "if test ${fdtfile} = ''; then " \ 64 "echo WARNING: Could not determine device tree to use; fi; \0" 65 66 #define CONFIG_EXTRA_ENV_SETTINGS \ 67 ENV_FINDFDT \ 68 ENV_DEVICE_SETTINGS \ 69 MEM_LAYOUT_SETTINGS \ 70 BOOTENV 71 72 #endif 73 74 /* OneNAND config */ 75 #define CONFIG_USE_ONENAND_BOARD_INIT 76 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 77 #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) 78 79 /* NAND config */ 80 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 81 #define CONFIG_SYS_NAND_PAGE_COUNT 64 82 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 83 #define CONFIG_SYS_NAND_OOBSIZE 64 84 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 85 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 86 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 87 10, 11, 12, 13, 14, 15, 16, 17, \ 88 18, 19, 20, 21, 22, 23, 24, 25, \ 89 26, 27, 28, 29, 30, 31, 32, 33, \ 90 34, 35, 36, 37, 38, 39, 40, 41, \ 91 42, 43, 44, 45, 46, 47, 48, 49, \ 92 50, 51, 52, 53, 54, 55, 56, 57, } 93 #define CONFIG_SYS_NAND_ECCSIZE 512 94 #define CONFIG_SYS_NAND_ECCBYTES 14 95 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 96 97 #endif /* __IGEP00X0_H */ 98