1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006. 4 * 5 * (C) Copyright 2010 6 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 7 */ 8 /* 9 * ve8313 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include <linux/stringify.h> 16 17 /* 18 * High Level Configuration Options 19 */ 20 #define CONFIG_E300 1 21 22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 23 24 /* 25 * On-board devices 26 * 27 */ 28 29 /* 30 * Device configurations 31 */ 32 33 /* 34 * DDR Setup 35 */ 36 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 37 38 /* 39 * Manually set up DDR parameters, as this board does not 40 * have the SPD connected to I2C. 41 */ 42 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 43 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 44 | CSCONFIG_AP \ 45 | CSCONFIG_ODT_RD_NEVER \ 46 | CSCONFIG_ODT_WR_ALL \ 47 | CSCONFIG_ROW_BIT_13 \ 48 | CSCONFIG_COL_BIT_10) 49 /* 0x80840102 */ 50 51 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 53 | (0 << TIMING_CFG0_WRT_SHIFT) \ 54 | (3 << TIMING_CFG0_RRT_SHIFT) \ 55 | (2 << TIMING_CFG0_WWT_SHIFT) \ 56 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 57 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 58 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 59 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 60 /* 0x0e720802 */ 61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 62 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 63 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 64 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 65 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 66 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 67 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 68 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 69 /* 0x26256222 */ 70 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 71 | (5 << TIMING_CFG2_CPO_SHIFT) \ 72 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 73 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 74 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 75 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 76 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 77 /* 0x029028c7 */ 78 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 79 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 80 /* 0x03202000 */ 81 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 82 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 83 | SDRAM_CFG_DBW_32) 84 /* 0x43080000 */ 85 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 86 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 87 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 88 /* 0x44400232 */ 89 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 90 91 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 92 /*0x02000000*/ 93 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 94 | DDRCDR_PZ_NOMZ \ 95 | DDRCDR_NZ_NOMZ \ 96 | DDRCDR_M_ODR) 97 /* 0x73000002 */ 98 99 /* 100 * FLASH on the Local Bus 101 */ 102 #define CONFIG_SYS_FLASH_BASE 0xFE000000 103 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 104 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 105 106 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 107 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 108 109 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 110 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 111 112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 113 114 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 115 #define CONFIG_SYS_RAMBOOT 116 #endif 117 118 #define CONFIG_SYS_INIT_RAM_LOCK 1 119 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 120 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 121 122 #define CONFIG_SYS_GBL_DATA_OFFSET \ 123 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 124 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 125 126 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 127 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 128 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 129 130 /* 131 * NAND settings 132 */ 133 #define CONFIG_SYS_NAND_BASE 0x61000000 134 #define CONFIG_SYS_MAX_NAND_DEVICE 1 135 #define CONFIG_NAND_FSL_ELBC 1 136 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 137 138 139 140 /* Still needed for spl_minimal.c */ 141 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM 142 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM 143 144 145 146 /* 147 * Serial Port 148 */ 149 #define CONFIG_SYS_NS16550_SERIAL 150 #define CONFIG_SYS_NS16550_REG_SIZE 1 151 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 152 153 #define CONFIG_SYS_BAUDRATE_TABLE \ 154 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 155 156 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 157 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 158 159 #if defined(CONFIG_PCI) 160 /* 161 * General PCI 162 * Addresses are mapped 1-1. 163 */ 164 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 165 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 166 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 167 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 168 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 169 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 170 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 171 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 172 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 173 174 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 175 #endif 176 177 /* 178 * TSEC 179 */ 180 181 #define CONFIG_TSEC1 182 #ifdef CONFIG_TSEC1 183 #define CONFIG_HAS_ETH0 184 #define CONFIG_TSEC1_NAME "TSEC1" 185 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 186 #define TSEC1_PHY_ADDR 0x01 187 #define TSEC1_FLAGS 0 188 #define TSEC1_PHYIDX 0 189 #endif 190 191 /* Options are: TSEC[0-1] */ 192 #define CONFIG_ETHPRIME "TSEC1" 193 194 /* 195 * Environment 196 */ 197 /* Address and size of Redundant Environment Sector */ 198 199 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 200 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 201 202 /* 203 * BOOTP options 204 */ 205 #define CONFIG_BOOTP_BOOTFILESIZE 206 207 /* 208 * Miscellaneous configurable options 209 */ 210 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 211 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 212 213 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 214 215 /* 216 * For booting Linux, the board info and command line data 217 * have to be in the first 256 MB of memory, since this is 218 * the maximum mapped by the Linux kernel during initialization. 219 */ 220 /* Initial Memory map for Linux*/ 221 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 222 223 /* System IO Config */ 224 #define CONFIG_SYS_SICRH (0x01000000 | \ 225 SICRH_ETSEC2_B | \ 226 SICRH_ETSEC2_C | \ 227 SICRH_ETSEC2_D | \ 228 SICRH_ETSEC2_E | \ 229 SICRH_ETSEC2_F | \ 230 SICRH_ETSEC2_G | \ 231 SICRH_TSOBI1 | \ 232 SICRH_TSOBI2) 233 /* 0x010fff03 */ 234 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 235 SICRL_SPI_A | \ 236 SICRL_SPI_B | \ 237 SICRL_SPI_C | \ 238 SICRL_SPI_D | \ 239 SICRL_ETSEC2_A) 240 /* 0x33fc0003) */ 241 242 #define CONFIG_NETDEV eth0 243 244 #define CONFIG_HOSTNAME "ve8313" 245 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 246 247 #define CONFIG_EXTRA_ENV_SETTINGS \ 248 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 249 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ 250 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 251 "u-boot_addr_r=100000\0" \ 252 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 253 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 254 " +${filesize};" \ 255 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 256 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ 257 " ${filesize};" \ 258 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 259 260 #endif /* __CONFIG_H */ 261