1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HABANALABS_H_ 9 #define HABANALABS_H_ 10 11 #include <linux/types.h> 12 #include <linux/ioctl.h> 13 14 /* 15 * Defines that are asic-specific but constitutes as ABI between kernel driver 16 * and userspace 17 */ 18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ 19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ 20 21 /* 22 * 128 SOBs reserved for collective wait 23 * 16 SOBs reserved for sync stream 24 */ 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 27 /* 28 * 64 monitors reserved for collective wait 29 * 8 monitors reserved for sync stream 30 */ 31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 32 33 /* 34 * Goya queue Numbering 35 * 36 * The external queues (PCI DMA channels) MUST be before the internal queues 37 * and each group (PCI DMA channels and internal) must be contiguous inside 38 * itself but there can be a gap between the two groups (although not 39 * recommended) 40 */ 41 42 enum goya_queue_id { 43 GOYA_QUEUE_ID_DMA_0 = 0, 44 GOYA_QUEUE_ID_DMA_1 = 1, 45 GOYA_QUEUE_ID_DMA_2 = 2, 46 GOYA_QUEUE_ID_DMA_3 = 3, 47 GOYA_QUEUE_ID_DMA_4 = 4, 48 GOYA_QUEUE_ID_CPU_PQ = 5, 49 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */ 50 GOYA_QUEUE_ID_TPC0 = 7, 51 GOYA_QUEUE_ID_TPC1 = 8, 52 GOYA_QUEUE_ID_TPC2 = 9, 53 GOYA_QUEUE_ID_TPC3 = 10, 54 GOYA_QUEUE_ID_TPC4 = 11, 55 GOYA_QUEUE_ID_TPC5 = 12, 56 GOYA_QUEUE_ID_TPC6 = 13, 57 GOYA_QUEUE_ID_TPC7 = 14, 58 GOYA_QUEUE_ID_SIZE 59 }; 60 61 /* 62 * Gaudi queue Numbering 63 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. 64 * Except one CPU queue, all the rest are internal queues. 65 */ 66 67 enum gaudi_queue_id { 68 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ 69 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ 70 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ 71 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ 72 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ 73 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ 74 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ 75 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ 76 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ 77 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ 78 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ 79 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ 80 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ 81 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ 82 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ 83 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ 84 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ 85 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ 86 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ 87 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ 88 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ 89 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */ 90 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */ 91 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */ 92 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */ 93 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ 94 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ 95 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ 96 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ 97 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ 98 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ 99 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ 100 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ 101 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ 102 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ 103 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ 104 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ 105 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ 106 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ 107 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ 108 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ 109 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ 110 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ 111 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ 112 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ 113 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ 114 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ 115 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ 116 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ 117 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ 118 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ 119 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ 120 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ 121 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ 122 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ 123 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ 124 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ 125 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ 126 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ 127 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ 128 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ 129 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ 130 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ 131 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ 132 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ 133 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ 134 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ 135 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ 136 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ 137 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ 138 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ 139 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ 140 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ 141 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ 142 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ 143 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ 144 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ 145 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ 146 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ 147 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ 148 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ 149 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ 150 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ 151 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ 152 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ 153 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ 154 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ 155 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ 156 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ 157 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ 158 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ 159 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ 160 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ 161 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ 162 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ 163 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ 164 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ 165 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ 166 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ 167 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ 168 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ 169 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ 170 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ 171 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ 172 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ 173 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ 174 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ 175 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ 176 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ 177 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ 178 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ 179 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ 180 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ 181 GAUDI_QUEUE_ID_SIZE 182 }; 183 184 /* 185 * Engine Numbering 186 * 187 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' 188 */ 189 190 enum goya_engine_id { 191 GOYA_ENGINE_ID_DMA_0 = 0, 192 GOYA_ENGINE_ID_DMA_1, 193 GOYA_ENGINE_ID_DMA_2, 194 GOYA_ENGINE_ID_DMA_3, 195 GOYA_ENGINE_ID_DMA_4, 196 GOYA_ENGINE_ID_MME_0, 197 GOYA_ENGINE_ID_TPC_0, 198 GOYA_ENGINE_ID_TPC_1, 199 GOYA_ENGINE_ID_TPC_2, 200 GOYA_ENGINE_ID_TPC_3, 201 GOYA_ENGINE_ID_TPC_4, 202 GOYA_ENGINE_ID_TPC_5, 203 GOYA_ENGINE_ID_TPC_6, 204 GOYA_ENGINE_ID_TPC_7, 205 GOYA_ENGINE_ID_SIZE 206 }; 207 208 enum gaudi_engine_id { 209 GAUDI_ENGINE_ID_DMA_0 = 0, 210 GAUDI_ENGINE_ID_DMA_1, 211 GAUDI_ENGINE_ID_DMA_2, 212 GAUDI_ENGINE_ID_DMA_3, 213 GAUDI_ENGINE_ID_DMA_4, 214 GAUDI_ENGINE_ID_DMA_5, 215 GAUDI_ENGINE_ID_DMA_6, 216 GAUDI_ENGINE_ID_DMA_7, 217 GAUDI_ENGINE_ID_MME_0, 218 GAUDI_ENGINE_ID_MME_1, 219 GAUDI_ENGINE_ID_MME_2, 220 GAUDI_ENGINE_ID_MME_3, 221 GAUDI_ENGINE_ID_TPC_0, 222 GAUDI_ENGINE_ID_TPC_1, 223 GAUDI_ENGINE_ID_TPC_2, 224 GAUDI_ENGINE_ID_TPC_3, 225 GAUDI_ENGINE_ID_TPC_4, 226 GAUDI_ENGINE_ID_TPC_5, 227 GAUDI_ENGINE_ID_TPC_6, 228 GAUDI_ENGINE_ID_TPC_7, 229 GAUDI_ENGINE_ID_NIC_0, 230 GAUDI_ENGINE_ID_NIC_1, 231 GAUDI_ENGINE_ID_NIC_2, 232 GAUDI_ENGINE_ID_NIC_3, 233 GAUDI_ENGINE_ID_NIC_4, 234 GAUDI_ENGINE_ID_NIC_5, 235 GAUDI_ENGINE_ID_NIC_6, 236 GAUDI_ENGINE_ID_NIC_7, 237 GAUDI_ENGINE_ID_NIC_8, 238 GAUDI_ENGINE_ID_NIC_9, 239 GAUDI_ENGINE_ID_SIZE 240 }; 241 242 /* 243 * ASIC specific PLL index 244 * 245 * Used to retrieve in frequency info of different IPs via 246 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be 247 * used as an index in struct hl_pll_frequency_info 248 */ 249 250 enum hl_goya_pll_index { 251 HL_GOYA_CPU_PLL = 0, 252 HL_GOYA_IC_PLL, 253 HL_GOYA_MC_PLL, 254 HL_GOYA_MME_PLL, 255 HL_GOYA_PCI_PLL, 256 HL_GOYA_EMMC_PLL, 257 HL_GOYA_TPC_PLL, 258 HL_GOYA_PLL_MAX 259 }; 260 261 enum hl_gaudi_pll_index { 262 HL_GAUDI_CPU_PLL = 0, 263 HL_GAUDI_PCI_PLL, 264 HL_GAUDI_SRAM_PLL, 265 HL_GAUDI_HBM_PLL, 266 HL_GAUDI_NIC_PLL, 267 HL_GAUDI_DMA_PLL, 268 HL_GAUDI_MESH_PLL, 269 HL_GAUDI_MME_PLL, 270 HL_GAUDI_TPC_PLL, 271 HL_GAUDI_IF_PLL, 272 HL_GAUDI_PLL_MAX 273 }; 274 275 /** 276 * enum hl_device_status - Device status information. 277 * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational. 278 * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset. 279 * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable. 280 * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled. 281 * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in 282 * progress. 283 * @HL_DEVICE_STATUS_LAST: Last status. 284 */ 285 enum hl_device_status { 286 HL_DEVICE_STATUS_OPERATIONAL, 287 HL_DEVICE_STATUS_IN_RESET, 288 HL_DEVICE_STATUS_MALFUNCTION, 289 HL_DEVICE_STATUS_NEEDS_RESET, 290 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 291 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION 292 }; 293 294 enum hl_server_type { 295 HL_SERVER_TYPE_UNKNOWN = 0, 296 HL_SERVER_GAUDI_HLS1 = 1, 297 HL_SERVER_GAUDI_HLS1H = 2, 298 HL_SERVER_GAUDI_TYPE1 = 3, 299 HL_SERVER_GAUDI_TYPE2 = 4 300 }; 301 302 /* Opcode for management ioctl 303 * 304 * HW_IP_INFO - Receive information about different IP blocks in the 305 * device. 306 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event 307 * occurred since the last hard reset. 308 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the 309 * specific context. This is relevant only for devices 310 * where the dram is managed by the kernel driver 311 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each 312 * internal engine. 313 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't 314 * require an open context. 315 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device 316 * over the last period specified by the user. 317 * The period can be between 100ms to 1s, in 318 * resolution of 100ms. The return value is a 319 * percentage of the utilization rate. 320 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each 321 * event occurred since the driver was loaded. 322 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate 323 * of the device in MHz. The maximum clock rate is 324 * configurable via sysfs parameter 325 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset 326 * operations performed on the device since the last 327 * time the driver was loaded. 328 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time 329 * for synchronization. 330 * HL_INFO_CS_COUNTERS - Retrieve command submission counters 331 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters 332 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason 333 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore 334 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption 335 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency 336 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls 337 */ 338 #define HL_INFO_HW_IP_INFO 0 339 #define HL_INFO_HW_EVENTS 1 340 #define HL_INFO_DRAM_USAGE 2 341 #define HL_INFO_HW_IDLE 3 342 #define HL_INFO_DEVICE_STATUS 4 343 #define HL_INFO_DEVICE_UTILIZATION 6 344 #define HL_INFO_HW_EVENTS_AGGREGATE 7 345 #define HL_INFO_CLK_RATE 8 346 #define HL_INFO_RESET_COUNT 9 347 #define HL_INFO_TIME_SYNC 10 348 #define HL_INFO_CS_COUNTERS 11 349 #define HL_INFO_PCI_COUNTERS 12 350 #define HL_INFO_CLK_THROTTLE_REASON 13 351 #define HL_INFO_SYNC_MANAGER 14 352 #define HL_INFO_TOTAL_ENERGY 15 353 #define HL_INFO_PLL_FREQUENCY 16 354 #define HL_INFO_POWER 17 355 #define HL_INFO_OPEN_STATS 18 356 357 #define HL_INFO_VERSION_MAX_LEN 128 358 #define HL_INFO_CARD_NAME_MAX_LEN 16 359 360 /** 361 * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC 362 * @sram_base_address: The first SRAM physical base address that is free to be 363 * used by the user. 364 * @dram_base_address: The first DRAM virtual or physical base address that is 365 * free to be used by the user. 366 * @dram_size: The DRAM size that is available to the user. 367 * @sram_size: The SRAM size that is available to the user. 368 * @num_of_events: The number of events that can be received from the f/w. This 369 * is needed so the user can what is the size of the h/w events 370 * array he needs to pass to the kernel when he wants to fetch 371 * the event counters. 372 * @device_id: PCI device ID of the ASIC. 373 * @module_id: Module ID of the ASIC for mezzanine cards in servers 374 * (From OCP spec). 375 * @first_available_interrupt_id: The first available interrupt ID for the user 376 * to be used when it works with user interrupts. 377 * @server_type: Server type that the Gaudi ASIC is currently installed in. 378 * The value is according to enum hl_server_type 379 * @cpld_version: CPLD version on the board. 380 * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. 381 * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. 382 * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. 383 * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler 384 * in some ASICs. 385 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant 386 * for Goya/Gaudi only. 387 * @dram_enabled: Whether the DRAM is enabled. 388 * @cpucp_version: The CPUCP f/w version. 389 * @card_name: The card name as passed by the f/w. 390 * @dram_page_size: The DRAM physical page size. 391 */ 392 struct hl_info_hw_ip_info { 393 __u64 sram_base_address; 394 __u64 dram_base_address; 395 __u64 dram_size; 396 __u32 sram_size; 397 __u32 num_of_events; 398 __u32 device_id; 399 __u32 module_id; 400 __u32 reserved; 401 __u16 first_available_interrupt_id; 402 __u16 server_type; 403 __u32 cpld_version; 404 __u32 psoc_pci_pll_nr; 405 __u32 psoc_pci_pll_nf; 406 __u32 psoc_pci_pll_od; 407 __u32 psoc_pci_pll_div_factor; 408 __u8 tpc_enabled_mask; 409 __u8 dram_enabled; 410 __u8 pad[2]; 411 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 412 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 413 __u64 reserved2; 414 __u64 dram_page_size; 415 }; 416 417 struct hl_info_dram_usage { 418 __u64 dram_free_mem; 419 __u64 ctx_dram_mem; 420 }; 421 422 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2 423 424 struct hl_info_hw_idle { 425 __u32 is_idle; 426 /* 427 * Bitmask of busy engines. 428 * Bits definition is according to `enum <chip>_enging_id'. 429 */ 430 __u32 busy_engines_mask; 431 432 /* 433 * Extended Bitmask of busy engines. 434 * Bits definition is according to `enum <chip>_enging_id'. 435 */ 436 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 437 }; 438 439 struct hl_info_device_status { 440 __u32 status; 441 __u32 pad; 442 }; 443 444 struct hl_info_device_utilization { 445 __u32 utilization; 446 __u32 pad; 447 }; 448 449 struct hl_info_clk_rate { 450 __u32 cur_clk_rate_mhz; 451 __u32 max_clk_rate_mhz; 452 }; 453 454 struct hl_info_reset_count { 455 __u32 hard_reset_cnt; 456 __u32 soft_reset_cnt; 457 }; 458 459 struct hl_info_time_sync { 460 __u64 device_time; 461 __u64 host_time; 462 }; 463 464 /** 465 * struct hl_info_pci_counters - pci counters 466 * @rx_throughput: PCI rx throughput KBps 467 * @tx_throughput: PCI tx throughput KBps 468 * @replay_cnt: PCI replay counter 469 */ 470 struct hl_info_pci_counters { 471 __u64 rx_throughput; 472 __u64 tx_throughput; 473 __u64 replay_cnt; 474 }; 475 476 #define HL_CLK_THROTTLE_POWER 0x1 477 #define HL_CLK_THROTTLE_THERMAL 0x2 478 479 /** 480 * struct hl_info_clk_throttle - clock throttling reason 481 * @clk_throttling_reason: each bit represents a clk throttling reason 482 */ 483 struct hl_info_clk_throttle { 484 __u32 clk_throttling_reason; 485 }; 486 487 /** 488 * struct hl_info_energy - device energy information 489 * @total_energy_consumption: total device energy consumption 490 */ 491 struct hl_info_energy { 492 __u64 total_energy_consumption; 493 }; 494 495 #define HL_PLL_NUM_OUTPUTS 4 496 497 struct hl_pll_frequency_info { 498 __u16 output[HL_PLL_NUM_OUTPUTS]; 499 }; 500 501 /** 502 * struct hl_open_stats_info - device open statistics information 503 * @open_counter: ever growing counter, increased on each successful dev open 504 * @last_open_period_ms: duration (ms) device was open last time 505 */ 506 struct hl_open_stats_info { 507 __u64 open_counter; 508 __u64 last_open_period_ms; 509 }; 510 511 /** 512 * struct hl_power_info - power information 513 * @power: power consumption 514 */ 515 struct hl_power_info { 516 __u64 power; 517 }; 518 519 /** 520 * struct hl_info_sync_manager - sync manager information 521 * @first_available_sync_object: first available sob 522 * @first_available_monitor: first available monitor 523 * @first_available_cq: first available cq 524 */ 525 struct hl_info_sync_manager { 526 __u32 first_available_sync_object; 527 __u32 first_available_monitor; 528 __u32 first_available_cq; 529 __u32 reserved; 530 }; 531 532 /** 533 * struct hl_info_cs_counters - command submission counters 534 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue 535 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue 536 * @total_parsing_drop_cnt: total dropped due to error in packet parsing 537 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing 538 * @total_queue_full_drop_cnt: total dropped due to queue full 539 * @ctx_queue_full_drop_cnt: context dropped due to queue full 540 * @total_device_in_reset_drop_cnt: total dropped due to device in reset 541 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset 542 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight 543 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight 544 * @total_validation_drop_cnt: total dropped due to validation error 545 * @ctx_validation_drop_cnt: context dropped due to validation error 546 */ 547 struct hl_info_cs_counters { 548 __u64 total_out_of_mem_drop_cnt; 549 __u64 ctx_out_of_mem_drop_cnt; 550 __u64 total_parsing_drop_cnt; 551 __u64 ctx_parsing_drop_cnt; 552 __u64 total_queue_full_drop_cnt; 553 __u64 ctx_queue_full_drop_cnt; 554 __u64 total_device_in_reset_drop_cnt; 555 __u64 ctx_device_in_reset_drop_cnt; 556 __u64 total_max_cs_in_flight_drop_cnt; 557 __u64 ctx_max_cs_in_flight_drop_cnt; 558 __u64 total_validation_drop_cnt; 559 __u64 ctx_validation_drop_cnt; 560 }; 561 562 enum gaudi_dcores { 563 HL_GAUDI_WS_DCORE, 564 HL_GAUDI_WN_DCORE, 565 HL_GAUDI_EN_DCORE, 566 HL_GAUDI_ES_DCORE 567 }; 568 569 /** 570 * struct hl_info_args - Main structure to retrieve device related information. 571 * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation 572 * mentioned in @op. 573 * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it 574 * limits how many bytes the kernel can write. For hw_events array, the size should be 575 * hl_info_hw_ip_info.num_of_events * sizeof(__u32). 576 * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details. 577 * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores). 578 * @ctx_id: Context ID of the user. Currently not in use. 579 * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms 580 * resolution. Currently not in use. 581 * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration. 582 * @pad: Padding to 64 bit. 583 */ 584 struct hl_info_args { 585 __u64 return_pointer; 586 __u32 return_size; 587 __u32 op; 588 589 union { 590 __u32 dcore_id; 591 __u32 ctx_id; 592 __u32 period_ms; 593 __u32 pll_index; 594 }; 595 596 __u32 pad; 597 }; 598 599 /* Opcode to create a new command buffer */ 600 #define HL_CB_OP_CREATE 0 601 /* Opcode to destroy previously created command buffer */ 602 #define HL_CB_OP_DESTROY 1 603 /* Opcode to retrieve information about a command buffer */ 604 #define HL_CB_OP_INFO 2 605 606 /* 2MB minus 32 bytes for 2xMSG_PROT */ 607 #define HL_MAX_CB_SIZE (0x200000 - 32) 608 609 /* Indicates whether the command buffer should be mapped to the device's MMU */ 610 #define HL_CB_FLAGS_MAP 0x1 611 612 struct hl_cb_in { 613 /* Handle of CB or 0 if we want to create one */ 614 __u64 cb_handle; 615 /* HL_CB_OP_* */ 616 __u32 op; 617 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that 618 * will be allocated, regardless of this parameter's value, is PAGE_SIZE 619 */ 620 __u32 cb_size; 621 /* Context ID - Currently not in use */ 622 __u32 ctx_id; 623 /* HL_CB_FLAGS_* */ 624 __u32 flags; 625 }; 626 627 struct hl_cb_out { 628 union { 629 /* Handle of CB */ 630 __u64 cb_handle; 631 632 /* Information about CB */ 633 struct { 634 /* Usage count of CB */ 635 __u32 usage_cnt; 636 __u32 pad; 637 }; 638 }; 639 }; 640 641 union hl_cb_args { 642 struct hl_cb_in in; 643 struct hl_cb_out out; 644 }; 645 646 /* HL_CS_CHUNK_FLAGS_ values 647 * 648 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: 649 * Indicates if the CB was allocated and mapped by userspace. 650 * User allocated CB is a command buffer allocated by the user, via malloc 651 * (or similar). After allocating the CB, the user invokes “memory ioctl” 652 * to map the user memory into a device virtual address. The user provides 653 * this address via the cb_handle field. The interface provides the 654 * ability to create a large CBs, Which aren’t limited to 655 * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues 656 * throughput. This CB allocation method also reduces the use of Linux 657 * DMA-able memory pool. Which are limited and used by other Linux 658 * sub-systems. 659 */ 660 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 661 662 /* 663 * This structure size must always be fixed to 64-bytes for backward 664 * compatibility 665 */ 666 struct hl_cs_chunk { 667 union { 668 /* For external queue, this represents a Handle of CB on the 669 * Host. 670 * For internal queue in Goya, this represents an SRAM or 671 * a DRAM address of the internal CB. In Gaudi, this might also 672 * represent a mapped host address of the CB. 673 * 674 * A mapped host address is in the device address space, after 675 * a host address was mapped by the device MMU. 676 */ 677 __u64 cb_handle; 678 679 /* Relevant only when HL_CS_FLAGS_WAIT or 680 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 681 * This holds address of array of u64 values that contain 682 * signal CS sequence numbers. The wait described by 683 * this job will listen on all those signals 684 * (wait event per signal) 685 */ 686 __u64 signal_seq_arr; 687 688 /* 689 * Relevant only when HL_CS_FLAGS_WAIT or 690 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 691 * along with HL_CS_FLAGS_ENCAP_SIGNALS. 692 * This is the CS sequence which has the encapsulated signals. 693 */ 694 __u64 encaps_signal_seq; 695 }; 696 697 /* Index of queue to put the CB on */ 698 __u32 queue_index; 699 700 union { 701 /* 702 * Size of command buffer with valid packets 703 * Can be smaller then actual CB size 704 */ 705 __u32 cb_size; 706 707 /* Relevant only when HL_CS_FLAGS_WAIT or 708 * HL_CS_FLAGS_COLLECTIVE_WAIT is set. 709 * Number of entries in signal_seq_arr 710 */ 711 __u32 num_signal_seq_arr; 712 713 /* Relevant only when HL_CS_FLAGS_WAIT or 714 * HL_CS_FLAGS_COLLECTIVE_WAIT is set along 715 * with HL_CS_FLAGS_ENCAP_SIGNALS 716 * This set the signals range that the user want to wait for 717 * out of the whole reserved signals range. 718 * e.g if the signals range is 20, and user don't want 719 * to wait for signal 8, so he set this offset to 7, then 720 * he call the API again with 9 and so on till 20. 721 */ 722 __u32 encaps_signal_offset; 723 }; 724 725 /* HL_CS_CHUNK_FLAGS_* */ 726 __u32 cs_chunk_flags; 727 728 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. 729 * This holds the collective engine ID. The wait described by this job 730 * will sync with this engine and with all NICs before completion. 731 */ 732 __u32 collective_engine_id; 733 734 /* Align structure to 64 bytes */ 735 __u32 pad[10]; 736 }; 737 738 /* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ 739 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 740 #define HL_CS_FLAGS_SIGNAL 0x2 741 #define HL_CS_FLAGS_WAIT 0x4 742 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 743 #define HL_CS_FLAGS_TIMESTAMP 0x20 744 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 745 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 746 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 747 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 748 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 749 750 /* 751 * The encapsulated signals CS is merged into the existing CS ioctls. 752 * In order to use this feature need to follow the below procedure: 753 * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 754 * the output of this API will be the SOB offset from CFG_BASE. 755 * this address will be used to patch CB cmds to do the signaling for this 756 * SOB by incrementing it's value. 757 * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 758 * CS type, note that this might fail if out-of-sync happened to the SOB 759 * value, in case other signaling request to the same SOB occurred between 760 * reserve-unreserve calls. 761 * 2. Use the staged CS to do the encapsulated signaling jobs. 762 * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 763 * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset 764 * field. This offset allows app to wait on part of the reserved signals. 765 * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag 766 * to wait for the encapsulated signals. 767 */ 768 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 769 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 770 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 771 772 #define HL_CS_STATUS_SUCCESS 0 773 774 #define HL_MAX_JOBS_PER_CS 512 775 776 struct hl_cs_in { 777 778 /* this holds address of array of hl_cs_chunk for restore phase */ 779 __u64 chunks_restore; 780 781 /* holds address of array of hl_cs_chunk for execution phase */ 782 __u64 chunks_execute; 783 784 union { 785 /* 786 * Sequence number of a staged submission CS 787 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and 788 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset. 789 */ 790 __u64 seq; 791 792 /* 793 * Encapsulated signals handle id 794 * Valid for two flows: 795 * 1. CS with encapsulated signals: 796 * when HL_CS_FLAGS_STAGED_SUBMISSION and 797 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 798 * and HL_CS_FLAGS_ENCAP_SIGNALS are set. 799 * 2. unreserve signals: 800 * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set. 801 */ 802 __u32 encaps_sig_handle_id; 803 804 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 805 struct { 806 /* Encapsulated signals number */ 807 __u32 encaps_signals_count; 808 809 /* Encapsulated signals queue index (stream) */ 810 __u32 encaps_signals_q_idx; 811 }; 812 }; 813 814 /* Number of chunks in restore phase array. Maximum number is 815 * HL_MAX_JOBS_PER_CS 816 */ 817 __u32 num_chunks_restore; 818 819 /* Number of chunks in execution array. Maximum number is 820 * HL_MAX_JOBS_PER_CS 821 */ 822 __u32 num_chunks_execute; 823 824 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT 825 * is set 826 */ 827 __u32 timeout; 828 829 /* HL_CS_FLAGS_* */ 830 __u32 cs_flags; 831 832 /* Context ID - Currently not in use */ 833 __u32 ctx_id; 834 }; 835 836 struct hl_cs_out { 837 union { 838 /* 839 * seq holds the sequence number of the CS to pass to wait 840 * ioctl. All values are valid except for 0 and ULLONG_MAX 841 */ 842 __u64 seq; 843 844 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 845 struct { 846 /* This is the resereved signal handle id */ 847 __u32 handle_id; 848 849 /* This is the signals count */ 850 __u32 count; 851 }; 852 }; 853 854 /* HL_CS_STATUS */ 855 __u32 status; 856 857 /* 858 * SOB base address offset 859 * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set 860 */ 861 __u32 sob_base_addr_offset; 862 }; 863 864 union hl_cs_args { 865 struct hl_cs_in in; 866 struct hl_cs_out out; 867 }; 868 869 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 870 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 871 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 872 873 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 874 875 struct hl_wait_cs_in { 876 union { 877 struct { 878 /* 879 * In case of wait_cs holds the CS sequence number. 880 * In case of wait for multi CS hold a user pointer to 881 * an array of CS sequence numbers 882 */ 883 __u64 seq; 884 /* Absolute timeout to wait for command submission 885 * in microseconds 886 */ 887 __u64 timeout_us; 888 }; 889 890 struct { 891 /* User address for completion comparison. 892 * upon interrupt, driver will compare the value pointed 893 * by this address with the supplied target value. 894 * in order not to perform any comparison, set address 895 * to all 1s. 896 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 897 */ 898 __u64 addr; 899 /* Target value for completion comparison */ 900 __u64 target; 901 }; 902 }; 903 904 /* Context ID - Currently not in use */ 905 __u32 ctx_id; 906 907 /* HL_WAIT_CS_FLAGS_* 908 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include 909 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order 910 * not to specify an interrupt id ,set mask to all 1s. 911 */ 912 __u32 flags; 913 914 /* Multi CS API info- valid entries in multi-CS array */ 915 __u8 seq_arr_len; 916 __u8 pad[3]; 917 918 /* Absolute timeout to wait for an interrupt in microseconds. 919 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 920 */ 921 __u32 interrupt_timeout_us; 922 }; 923 924 #define HL_WAIT_CS_STATUS_COMPLETED 0 925 #define HL_WAIT_CS_STATUS_BUSY 1 926 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 927 #define HL_WAIT_CS_STATUS_ABORTED 3 928 929 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 930 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 931 932 struct hl_wait_cs_out { 933 /* HL_WAIT_CS_STATUS_* */ 934 __u32 status; 935 /* HL_WAIT_CS_STATUS_FLAG* */ 936 __u32 flags; 937 /* 938 * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set 939 * for wait_cs: timestamp of CS completion 940 * for wait_multi_cs: timestamp of FIRST CS completion 941 */ 942 __s64 timestamp_nsec; 943 /* multi CS completion bitmap */ 944 __u32 cs_completion_map; 945 __u32 pad; 946 }; 947 948 union hl_wait_cs_args { 949 struct hl_wait_cs_in in; 950 struct hl_wait_cs_out out; 951 }; 952 953 /* Opcode to allocate device memory */ 954 #define HL_MEM_OP_ALLOC 0 955 /* Opcode to free previously allocated device memory */ 956 #define HL_MEM_OP_FREE 1 957 /* Opcode to map host and device memory */ 958 #define HL_MEM_OP_MAP 2 959 /* Opcode to unmap previously mapped host and device memory */ 960 #define HL_MEM_OP_UNMAP 3 961 /* Opcode to map a hw block */ 962 #define HL_MEM_OP_MAP_BLOCK 4 963 /* Opcode to create DMA-BUF object for an existing device memory allocation 964 * and to export an FD of that DMA-BUF back to the caller 965 */ 966 #define HL_MEM_OP_EXPORT_DMABUF_FD 5 967 968 /* Memory flags */ 969 #define HL_MEM_CONTIGUOUS 0x1 970 #define HL_MEM_SHARED 0x2 971 #define HL_MEM_USERPTR 0x4 972 #define HL_MEM_FORCE_HINT 0x8 973 974 struct hl_mem_in { 975 union { 976 /* HL_MEM_OP_ALLOC- allocate device memory */ 977 struct { 978 /* Size to alloc */ 979 __u64 mem_size; 980 } alloc; 981 982 /* HL_MEM_OP_FREE - free device memory */ 983 struct { 984 /* Handle returned from HL_MEM_OP_ALLOC */ 985 __u64 handle; 986 } free; 987 988 /* HL_MEM_OP_MAP - map device memory */ 989 struct { 990 /* 991 * Requested virtual address of mapped memory. 992 * The driver will try to map the requested region to 993 * this hint address, as long as the address is valid 994 * and not already mapped. The user should check the 995 * returned address of the IOCTL to make sure he got 996 * the hint address. Passing 0 here means that the 997 * driver will choose the address itself. 998 */ 999 __u64 hint_addr; 1000 /* Handle returned from HL_MEM_OP_ALLOC */ 1001 __u64 handle; 1002 } map_device; 1003 1004 /* HL_MEM_OP_MAP - map host memory */ 1005 struct { 1006 /* Address of allocated host memory */ 1007 __u64 host_virt_addr; 1008 /* 1009 * Requested virtual address of mapped memory. 1010 * The driver will try to map the requested region to 1011 * this hint address, as long as the address is valid 1012 * and not already mapped. The user should check the 1013 * returned address of the IOCTL to make sure he got 1014 * the hint address. Passing 0 here means that the 1015 * driver will choose the address itself. 1016 */ 1017 __u64 hint_addr; 1018 /* Size of allocated host memory */ 1019 __u64 mem_size; 1020 } map_host; 1021 1022 /* HL_MEM_OP_MAP_BLOCK - map a hw block */ 1023 struct { 1024 /* 1025 * HW block address to map, a handle and size will be 1026 * returned to the user and will be used to mmap the 1027 * relevant block. Only addresses from configuration 1028 * space are allowed. 1029 */ 1030 __u64 block_addr; 1031 } map_block; 1032 1033 /* HL_MEM_OP_UNMAP - unmap host memory */ 1034 struct { 1035 /* Virtual address returned from HL_MEM_OP_MAP */ 1036 __u64 device_virt_addr; 1037 } unmap; 1038 1039 /* HL_MEM_OP_EXPORT_DMABUF_FD */ 1040 struct { 1041 /* Handle returned from HL_MEM_OP_ALLOC. In Gaudi, 1042 * where we don't have MMU for the device memory, the 1043 * driver expects a physical address (instead of 1044 * a handle) in the device memory space. 1045 */ 1046 __u64 handle; 1047 /* Size of memory allocation. Relevant only for GAUDI */ 1048 __u64 mem_size; 1049 } export_dmabuf_fd; 1050 }; 1051 1052 /* HL_MEM_OP_* */ 1053 __u32 op; 1054 /* HL_MEM_* flags. 1055 * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode, this field holds the 1056 * DMA-BUF file/FD flags. 1057 */ 1058 __u32 flags; 1059 /* Context ID - Currently not in use */ 1060 __u32 ctx_id; 1061 __u32 pad; 1062 }; 1063 1064 struct hl_mem_out { 1065 union { 1066 /* 1067 * Used for HL_MEM_OP_MAP as the virtual address that was 1068 * assigned in the device VA space. 1069 * A value of 0 means the requested operation failed. 1070 */ 1071 __u64 device_virt_addr; 1072 1073 /* 1074 * Used in HL_MEM_OP_ALLOC 1075 * This is the assigned handle for the allocated memory 1076 */ 1077 __u64 handle; 1078 1079 struct { 1080 /* 1081 * Used in HL_MEM_OP_MAP_BLOCK. 1082 * This is the assigned handle for the mapped block 1083 */ 1084 __u64 block_handle; 1085 1086 /* 1087 * Used in HL_MEM_OP_MAP_BLOCK 1088 * This is the size of the mapped block 1089 */ 1090 __u32 block_size; 1091 1092 __u32 pad; 1093 }; 1094 1095 /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the 1096 * DMA-BUF object that was created to describe a memory 1097 * allocation on the device's memory space. The FD should be 1098 * passed to the importer driver 1099 */ 1100 __s32 fd; 1101 }; 1102 }; 1103 1104 union hl_mem_args { 1105 struct hl_mem_in in; 1106 struct hl_mem_out out; 1107 }; 1108 1109 #define HL_DEBUG_MAX_AUX_VALUES 10 1110 1111 struct hl_debug_params_etr { 1112 /* Address in memory to allocate buffer */ 1113 __u64 buffer_address; 1114 1115 /* Size of buffer to allocate */ 1116 __u64 buffer_size; 1117 1118 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1119 __u32 sink_mode; 1120 __u32 pad; 1121 }; 1122 1123 struct hl_debug_params_etf { 1124 /* Address in memory to allocate buffer */ 1125 __u64 buffer_address; 1126 1127 /* Size of buffer to allocate */ 1128 __u64 buffer_size; 1129 1130 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1131 __u32 sink_mode; 1132 __u32 pad; 1133 }; 1134 1135 struct hl_debug_params_stm { 1136 /* Two bit masks for HW event and Stimulus Port */ 1137 __u64 he_mask; 1138 __u64 sp_mask; 1139 1140 /* Trace source ID */ 1141 __u32 id; 1142 1143 /* Frequency for the timestamp register */ 1144 __u32 frequency; 1145 }; 1146 1147 struct hl_debug_params_bmon { 1148 /* Two address ranges that the user can request to filter */ 1149 __u64 start_addr0; 1150 __u64 addr_mask0; 1151 1152 __u64 start_addr1; 1153 __u64 addr_mask1; 1154 1155 /* Capture window configuration */ 1156 __u32 bw_win; 1157 __u32 win_capture; 1158 1159 /* Trace source ID */ 1160 __u32 id; 1161 __u32 pad; 1162 }; 1163 1164 struct hl_debug_params_spmu { 1165 /* Event types selection */ 1166 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 1167 1168 /* Number of event types selection */ 1169 __u32 event_types_num; 1170 __u32 pad; 1171 }; 1172 1173 /* Opcode for ETR component */ 1174 #define HL_DEBUG_OP_ETR 0 1175 /* Opcode for ETF component */ 1176 #define HL_DEBUG_OP_ETF 1 1177 /* Opcode for STM component */ 1178 #define HL_DEBUG_OP_STM 2 1179 /* Opcode for FUNNEL component */ 1180 #define HL_DEBUG_OP_FUNNEL 3 1181 /* Opcode for BMON component */ 1182 #define HL_DEBUG_OP_BMON 4 1183 /* Opcode for SPMU component */ 1184 #define HL_DEBUG_OP_SPMU 5 1185 /* Opcode for timestamp (deprecated) */ 1186 #define HL_DEBUG_OP_TIMESTAMP 6 1187 /* Opcode for setting the device into or out of debug mode. The enable 1188 * variable should be 1 for enabling debug mode and 0 for disabling it 1189 */ 1190 #define HL_DEBUG_OP_SET_MODE 7 1191 1192 struct hl_debug_args { 1193 /* 1194 * Pointer to user input structure. 1195 * This field is relevant to specific opcodes. 1196 */ 1197 __u64 input_ptr; 1198 /* Pointer to user output structure */ 1199 __u64 output_ptr; 1200 /* Size of user input structure */ 1201 __u32 input_size; 1202 /* Size of user output structure */ 1203 __u32 output_size; 1204 /* HL_DEBUG_OP_* */ 1205 __u32 op; 1206 /* 1207 * Register index in the component, taken from the debug_regs_index enum 1208 * in the various ASIC header files 1209 */ 1210 __u32 reg_idx; 1211 /* Enable/disable */ 1212 __u32 enable; 1213 /* Context ID - Currently not in use */ 1214 __u32 ctx_id; 1215 }; 1216 1217 /* 1218 * Various information operations such as: 1219 * - H/W IP information 1220 * - Current dram usage 1221 * 1222 * The user calls this IOCTL with an opcode that describes the required 1223 * information. The user should supply a pointer to a user-allocated memory 1224 * chunk, which will be filled by the driver with the requested information. 1225 * 1226 * The user supplies the maximum amount of size to copy into the user's memory, 1227 * in order to prevent data corruption in case of differences between the 1228 * definitions of structures in kernel and userspace, e.g. in case of old 1229 * userspace and new kernel driver 1230 */ 1231 #define HL_IOCTL_INFO \ 1232 _IOWR('H', 0x01, struct hl_info_args) 1233 1234 /* 1235 * Command Buffer 1236 * - Request a Command Buffer 1237 * - Destroy a Command Buffer 1238 * 1239 * The command buffers are memory blocks that reside in DMA-able address 1240 * space and are physically contiguous so they can be accessed by the device 1241 * directly. They are allocated using the coherent DMA API. 1242 * 1243 * When creating a new CB, the IOCTL returns a handle of it, and the user-space 1244 * process needs to use that handle to mmap the buffer so it can access them. 1245 * 1246 * In some instances, the device must access the command buffer through the 1247 * device's MMU, and thus its memory should be mapped. In these cases, user can 1248 * indicate the driver that such a mapping is required. 1249 * The resulting device virtual address will be used internally by the driver, 1250 * and won't be returned to user. 1251 * 1252 */ 1253 #define HL_IOCTL_CB \ 1254 _IOWR('H', 0x02, union hl_cb_args) 1255 1256 /* 1257 * Command Submission 1258 * 1259 * To submit work to the device, the user need to call this IOCTL with a set 1260 * of JOBS. That set of JOBS constitutes a CS object. 1261 * Each JOB will be enqueued on a specific queue, according to the user's input. 1262 * There can be more then one JOB per queue. 1263 * 1264 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase 1265 * and a second set is for "execution" phase. 1266 * The JOBS on the "restore" phase are enqueued only after context-switch 1267 * (or if its the first CS for this context). The user can also order the 1268 * driver to run the "restore" phase explicitly 1269 * 1270 * There are two types of queues - external and internal. External queues 1271 * are DMA queues which transfer data from/to the Host. All other queues are 1272 * internal. The driver will get completion notifications from the device only 1273 * on JOBS which are enqueued in the external queues. 1274 * 1275 * For jobs on external queues, the user needs to create command buffers 1276 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on 1277 * internal queues, the user needs to prepare a "command buffer" with packets 1278 * on either the device SRAM/DRAM or the host, and give the device address of 1279 * that buffer to the CS ioctl. 1280 * 1281 * This IOCTL is asynchronous in regard to the actual execution of the CS. This 1282 * means it returns immediately after ALL the JOBS were enqueued on their 1283 * relevant queues. Therefore, the user mustn't assume the CS has been completed 1284 * or has even started to execute. 1285 * 1286 * Upon successful enqueue, the IOCTL returns a sequence number which the user 1287 * can use with the "Wait for CS" IOCTL to check whether the handle's CS 1288 * external JOBS have been completed. Note that if the CS has internal JOBS 1289 * which can execute AFTER the external JOBS have finished, the driver might 1290 * report that the CS has finished executing BEFORE the internal JOBS have 1291 * actually finished executing. 1292 * 1293 * Even though the sequence number increments per CS, the user can NOT 1294 * automatically assume that if CS with sequence number N finished, then CS 1295 * with sequence number N-1 also finished. The user can make this assumption if 1296 * and only if CS N and CS N-1 are exactly the same (same CBs for the same 1297 * queues). 1298 */ 1299 #define HL_IOCTL_CS \ 1300 _IOWR('H', 0x03, union hl_cs_args) 1301 1302 /* 1303 * Wait for Command Submission 1304 * 1305 * The user can call this IOCTL with a handle it received from the CS IOCTL 1306 * to wait until the handle's CS has finished executing. The user will wait 1307 * inside the kernel until the CS has finished or until the user-requested 1308 * timeout has expired. 1309 * 1310 * If the timeout value is 0, the driver won't sleep at all. It will check 1311 * the status of the CS and return immediately 1312 * 1313 * The return value of the IOCTL is a standard Linux error code. The possible 1314 * values are: 1315 * 1316 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal 1317 * that the user process received 1318 * ETIMEDOUT - The CS has caused a timeout on the device 1319 * EIO - The CS was aborted (usually because the device was reset) 1320 * ENODEV - The device wants to do hard-reset (so user need to close FD) 1321 * 1322 * The driver also returns a custom define in case the IOCTL call returned 0. 1323 * The define can be one of the following: 1324 * 1325 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0) 1326 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0) 1327 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device 1328 * (ETIMEDOUT) 1329 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the 1330 * device was reset (EIO) 1331 */ 1332 1333 #define HL_IOCTL_WAIT_CS \ 1334 _IOWR('H', 0x04, union hl_wait_cs_args) 1335 1336 /* 1337 * Memory 1338 * - Map host memory to device MMU 1339 * - Unmap host memory from device MMU 1340 * 1341 * This IOCTL allows the user to map host memory to the device MMU 1342 * 1343 * For host memory, the IOCTL doesn't allocate memory. The user is supposed 1344 * to allocate the memory in user-space (malloc/new). The driver pins the 1345 * physical pages (up to the allowed limit by the OS), assigns a virtual 1346 * address in the device VA space and initializes the device MMU. 1347 * 1348 * There is an option for the user to specify the requested virtual address. 1349 * 1350 */ 1351 #define HL_IOCTL_MEMORY \ 1352 _IOWR('H', 0x05, union hl_mem_args) 1353 1354 /* 1355 * Debug 1356 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces 1357 * 1358 * This IOCTL allows the user to get debug traces from the chip. 1359 * 1360 * Before the user can send configuration requests of the various 1361 * debug/profile engines, it needs to set the device into debug mode. 1362 * This is because the debug/profile infrastructure is shared component in the 1363 * device and we can't allow multiple users to access it at the same time. 1364 * 1365 * Once a user set the device into debug mode, the driver won't allow other 1366 * users to "work" with the device, i.e. open a FD. If there are multiple users 1367 * opened on the device, the driver won't allow any user to debug the device. 1368 * 1369 * For each configuration request, the user needs to provide the register index 1370 * and essential data such as buffer address and size. 1371 * 1372 * Once the user has finished using the debug/profile engines, he should 1373 * set the device into non-debug mode, i.e. disable debug mode. 1374 * 1375 * The driver can decide to "kick out" the user if he abuses this interface. 1376 * 1377 */ 1378 #define HL_IOCTL_DEBUG \ 1379 _IOWR('H', 0x06, struct hl_debug_args) 1380 1381 #define HL_COMMAND_START 0x01 1382 #define HL_COMMAND_END 0x07 1383 1384 #endif /* HABANALABS_H_ */ 1385