1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #ifndef __INTEL_DE_H__
7 #define __INTEL_DE_H__
8
9 #include "i915_drv.h"
10 #include "i915_reg.h"
11 #include "i915_trace.h"
12 #include "intel_uncore.h"
13
14 static inline u32
intel_de_read(struct drm_i915_private * i915,i915_reg_t reg)15 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
16 {
17 return intel_uncore_read(&i915->uncore, reg);
18 }
19
20 static inline void
intel_de_posting_read(struct drm_i915_private * i915,i915_reg_t reg)21 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
22 {
23 intel_uncore_posting_read(&i915->uncore, reg);
24 }
25
26 static inline void
intel_de_write(struct drm_i915_private * i915,i915_reg_t reg,u32 val)27 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
28 {
29 intel_uncore_write(&i915->uncore, reg, val);
30 }
31
32 static inline void
intel_de_rmw(struct drm_i915_private * i915,i915_reg_t reg,u32 clear,u32 set)33 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
34 {
35 intel_uncore_rmw(&i915->uncore, reg, clear, set);
36 }
37
38 static inline int
intel_de_wait_for_register(struct drm_i915_private * i915,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout)39 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
40 u32 mask, u32 value, unsigned int timeout)
41 {
42 return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
43 }
44
45 static inline int
intel_de_wait_for_set(struct drm_i915_private * i915,i915_reg_t reg,u32 mask,unsigned int timeout)46 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
47 u32 mask, unsigned int timeout)
48 {
49 return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
50 }
51
52 static inline int
intel_de_wait_for_clear(struct drm_i915_private * i915,i915_reg_t reg,u32 mask,unsigned int timeout)53 intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
54 u32 mask, unsigned int timeout)
55 {
56 return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
57 }
58
59 /*
60 * Unlocked mmio-accessors, think carefully before using these.
61 *
62 * Certain architectures will die if the same cacheline is concurrently accessed
63 * by different clients (e.g. on Ivybridge). Access to registers should
64 * therefore generally be serialised, by either the dev_priv->uncore.lock or
65 * a more localised lock guarding all access to that bank of registers.
66 */
67 static inline u32
intel_de_read_fw(struct drm_i915_private * i915,i915_reg_t reg)68 intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
69 {
70 u32 val;
71
72 val = intel_uncore_read_fw(&i915->uncore, reg);
73 trace_i915_reg_rw(false, reg, val, sizeof(val), true);
74
75 return val;
76 }
77
78 static inline void
intel_de_write_fw(struct drm_i915_private * i915,i915_reg_t reg,u32 val)79 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
80 {
81 trace_i915_reg_rw(true, reg, val, sizeof(val), true);
82 intel_uncore_write_fw(&i915->uncore, reg, val);
83 }
84
85 #endif /* __INTEL_DE_H__ */
86