1 /*
2  * High Level Configuration Options
3  */
4 #define CONFIG_E300		1	/* E300 family */
5 
6 #define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
7 
8 /*
9  * System Clock Setup
10  */
11 #define CONFIG_83XX_CLKIN		66000000
12 #define CONFIG_SYS_CLK_FREQ		66000000
13 #define CONFIG_83XX_PCICLK		66000000
14 
15 /* QE microcode/firmware address */
16 /* between the u-boot partition and env */
17 #ifndef CONFIG_SYS_QE_FW_ADDR
18 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
19 #endif
20 
21 /*
22  * System IO Config
23  */
24 /* 0x14000180 SICR_1 */
25 #ifndef CONFIG_SYS_SICRL
26 #define CONFIG_SYS_SICRL (0			\
27 		| SICR_1_UART1_UART1RTS		\
28 		| SICR_1_I2C_CKSTOP		\
29 		| SICR_1_IRQ_A_IRQ		\
30 		| SICR_1_IRQ_B_IRQ		\
31 		| SICR_1_GPIO_A_GPIO		\
32 		| SICR_1_GPIO_B_GPIO		\
33 		| SICR_1_GPIO_C_GPIO		\
34 		| SICR_1_GPIO_D_GPIO		\
35 		| SICR_1_GPIO_E_GPIO		\
36 		| SICR_1_GPIO_F_GPIO		\
37 		| SICR_1_USB_A_UART2S		\
38 		| SICR_1_USB_B_UART2RTS		\
39 		| SICR_1_FEC1_FEC1		\
40 		| SICR_1_FEC2_FEC2		\
41 		)
42 #endif
43 
44 /* 0x00080400 SICR_2 */
45 #define CONFIG_SYS_SICRH (0			\
46 		| SICR_2_FEC3_FEC3		\
47 		| SICR_2_HDLC1_A_HDLC1		\
48 		| SICR_2_ELBC_A_LA		\
49 		| SICR_2_ELBC_B_LCLK		\
50 		| SICR_2_HDLC2_A_HDLC2		\
51 		| SICR_2_USB_D_GPIO		\
52 		| SICR_2_PCI_PCI		\
53 		| SICR_2_HDLC1_B_HDLC1		\
54 		| SICR_2_HDLC1_C_HDLC1		\
55 		| SICR_2_HDLC2_B_GPIO		\
56 		| SICR_2_HDLC2_C_HDLC2		\
57 		| SICR_2_QUIESCE_B		\
58 		)
59 
60 /* GPR_1 */
61 #define CONFIG_SYS_GPR1  0x50008060
62 
63 #define CONFIG_SYS_GP1DIR 0x00000000
64 #define CONFIG_SYS_GP1ODR 0x00000000
65 #define CONFIG_SYS_GP2DIR 0xFF000000
66 #define CONFIG_SYS_GP2ODR 0x00000000
67 
68 #define CONFIG_SYS_DDRCDR (\
69 	DDRCDR_EN | \
70 	DDRCDR_PZ_MAXZ | \
71 	DDRCDR_NZ_MAXZ | \
72 	DDRCDR_M_ODR)
73 
74 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
75 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
76 					 SDRAM_CFG_32_BE | \
77 					 SDRAM_CFG_SREN | \
78 					 SDRAM_CFG_HSE)
79 
80 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
81 #define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
82 #define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
83 				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
84 
85 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
86 					 CSCONFIG_ODT_RD_NEVER | \
87 					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
88 					 CSCONFIG_ROW_BIT_13 | \
89 					 CSCONFIG_COL_BIT_10)
90 
91 #define CONFIG_SYS_DDR_MODE	0x47860242
92 #define CONFIG_SYS_DDR_MODE2	0x8080c000
93 
94 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
95 				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
96 				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
97 				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
98 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
99 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
100 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
101 				 (0 << TIMING_CFG0_RWT_SHIFT))
102 
103 #define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
104 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
105 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
106 				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
107 				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
108 				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
109 				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
110 				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
111 
112 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
113 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
114 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
115 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
116 				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
117 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
118 				 (5 << TIMING_CFG2_CPO_SHIFT))
119 
120 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
121 
122 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
123 #define CONFIG_SYS_KMBEC_FPGA_SIZE	128
124 
125 /* EEprom support */
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
127 
128 /* ethernet port connected to piggy (UEC2) */
129 #define CONFIG_HAS_ETH1
130 #define CONFIG_UEC_ETH2
131 #define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
132 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
133 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
134 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
135 #define CONFIG_SYS_UEC2_PHY_ADDR	0
136 #define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
137 #define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
138