1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <cortex_a7.h>
11#include <cpu_macros.S>
12
13	.macro assert_cache_enabled
14#if ENABLE_ASSERTIONS
15		ldcopr	r0, SCTLR
16		tst	r0, #SCTLR_C_BIT
17		ASM_ASSERT(eq)
18#endif
19	.endm
20
21func cortex_a7_disable_smp
22	ldcopr	r0, ACTLR
23	bic	r0, #CORTEX_A7_ACTLR_SMP_BIT
24	stcopr	r0, ACTLR
25	isb
26	dsb	sy
27	bx	lr
28endfunc cortex_a7_disable_smp
29
30func cortex_a7_enable_smp
31	ldcopr	r0, ACTLR
32	orr	r0, #CORTEX_A7_ACTLR_SMP_BIT
33	stcopr	r0, ACTLR
34	isb
35	bx	lr
36endfunc cortex_a7_enable_smp
37
38func cortex_a7_reset_func
39	b	cortex_a7_enable_smp
40endfunc cortex_a7_reset_func
41
42func cortex_a7_core_pwr_dwn
43	push	{r12, lr}
44
45	assert_cache_enabled
46
47	/* Flush L1 cache */
48	mov	r0, #DC_OP_CISW
49	bl	dcsw_op_level1
50
51	/* Exit cluster coherency */
52	pop	{r12, lr}
53	b	cortex_a7_disable_smp
54endfunc cortex_a7_core_pwr_dwn
55
56func cortex_a7_cluster_pwr_dwn
57	push	{r12, lr}
58
59	assert_cache_enabled
60
61	/* Flush L1 caches */
62	mov	r0, #DC_OP_CISW
63	bl	dcsw_op_level1
64
65	bl	plat_disable_acp
66
67	/* Exit cluster coherency */
68	pop	{r12, lr}
69	b	cortex_a7_disable_smp
70endfunc cortex_a7_cluster_pwr_dwn
71
72#if REPORT_ERRATA
73/*
74 * Errata printing function for Cortex-A7. Must follow AAPCS.
75 */
76func cortex_a7_errata_report
77	bx	lr
78endfunc cortex_a7_errata_report
79#endif
80
81declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
82	cortex_a7_reset_func, \
83	cortex_a7_core_pwr_dwn, \
84	cortex_a7_cluster_pwr_dwn
85