1/*
2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <arch.h>
7#include <asm_macros.S>
8#include <common/bl_common.h>
9#include <cortex_a73.h>
10#include <cpu_macros.S>
11#include <plat_macros.S>
12
13	/* ---------------------------------------------
14	 * Disable L1 data cache
15	 * ---------------------------------------------
16	 */
17func cortex_a73_disable_dcache
18	mrs	x1, sctlr_el3
19	bic	x1, x1, #SCTLR_C_BIT
20	msr	sctlr_el3, x1
21	isb
22	ret
23endfunc cortex_a73_disable_dcache
24
25	/* ---------------------------------------------
26	 * Disable intra-cluster coherency
27	 * ---------------------------------------------
28	 */
29func cortex_a73_disable_smp
30	mrs	x0, CORTEX_A73_CPUECTLR_EL1
31	bic	x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
32	msr	CORTEX_A73_CPUECTLR_EL1, x0
33	isb
34	dsb	sy
35	ret
36endfunc cortex_a73_disable_smp
37
38	/* ---------------------------------------------------
39	 * Errata Workaround for Cortex A73 Errata #852427.
40	 * This applies only to revision r0p0 of Cortex A73.
41	 * Inputs:
42	 * x0: variant[4:7] and revision[0:3] of current cpu.
43	 * Shall clobber: x0-x17
44	 * ---------------------------------------------------
45	 */
46func errata_a73_852427_wa
47	/*
48	 * Compare x0 against revision r0p0
49	 */
50	mov	x17, x30
51	bl	check_errata_852427
52	cbz	x0, 1f
53	mrs	x1, CORTEX_A73_DIAGNOSTIC_REGISTER
54	orr	x1, x1, #(1 << 12)
55	msr	CORTEX_A73_DIAGNOSTIC_REGISTER, x1
56	isb
571:
58	ret	x17
59endfunc errata_a73_852427_wa
60
61func check_errata_852427
62	mov	x1, #0x00
63	b	cpu_rev_var_ls
64endfunc check_errata_852427
65
66	/* ---------------------------------------------------
67	 * Errata Workaround for Cortex A73 Errata #855423.
68	 * This applies only to revision <= r0p1 of Cortex A73.
69	 * Inputs:
70	 * x0: variant[4:7] and revision[0:3] of current cpu.
71	 * Shall clobber: x0-x17
72	 * ---------------------------------------------------
73	 */
74func errata_a73_855423_wa
75	/*
76	 * Compare x0 against revision r0p1
77	 */
78	mov	x17, x30
79	bl	check_errata_855423
80	cbz	x0, 1f
81	mrs	x1, CORTEX_A73_IMP_DEF_REG2
82	orr	x1, x1, #(1 << 7)
83	msr	CORTEX_A73_IMP_DEF_REG2, x1
84	isb
851:
86	ret	x17
87endfunc errata_a73_855423_wa
88
89func check_errata_855423
90	mov	x1, #0x01
91	b	cpu_rev_var_ls
92endfunc check_errata_855423
93
94	/* -------------------------------------------------
95	 * The CPU Ops reset function for Cortex-A73.
96	 * -------------------------------------------------
97	 */
98
99func cortex_a73_reset_func
100	mov	x19, x30
101	bl	cpu_get_rev_var
102	mov	x18, x0
103
104#if ERRATA_A73_852427
105	mov	x0, x18
106	bl	errata_a73_852427_wa
107#endif
108
109#if ERRATA_A73_855423
110	mov	x0, x18
111	bl	errata_a73_855423_wa
112#endif
113
114#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
115	cpu_check_csv2	x0, 1f
116	adr	x0, wa_cve_2017_5715_bpiall_vbar
117	msr	vbar_el3, x0
118	/* isb will be performed before returning from this function */
1191:
120#endif
121
122#if WORKAROUND_CVE_2018_3639
123	mrs	x0, CORTEX_A73_IMP_DEF_REG1
124	orr	x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
125	msr	CORTEX_A73_IMP_DEF_REG1, x0
126	isb
127#endif
128
129	/* ---------------------------------------------
130	 * Enable the SMP bit.
131	 * Clobbers : x0
132	 * ---------------------------------------------
133	 */
134	mrs	x0, CORTEX_A73_CPUECTLR_EL1
135	orr	x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
136	msr	CORTEX_A73_CPUECTLR_EL1, x0
137	isb
138	ret	x19
139endfunc cortex_a73_reset_func
140
141func cortex_a73_core_pwr_dwn
142	mov	x18, x30
143
144	/* ---------------------------------------------
145	 * Turn off caches.
146	 * ---------------------------------------------
147	 */
148	bl	cortex_a73_disable_dcache
149
150	/* ---------------------------------------------
151	 * Flush L1 caches.
152	 * ---------------------------------------------
153	 */
154	mov	x0, #DCCISW
155	bl	dcsw_op_level1
156
157	/* ---------------------------------------------
158	 * Come out of intra cluster coherency
159	 * ---------------------------------------------
160	 */
161	mov	x30, x18
162	b	cortex_a73_disable_smp
163endfunc cortex_a73_core_pwr_dwn
164
165func cortex_a73_cluster_pwr_dwn
166	mov	x18, x30
167
168	/* ---------------------------------------------
169	 * Turn off caches.
170	 * ---------------------------------------------
171	 */
172	bl	cortex_a73_disable_dcache
173
174	/* ---------------------------------------------
175	 * Flush L1 caches.
176	 * ---------------------------------------------
177	 */
178	mov	x0, #DCCISW
179	bl	dcsw_op_level1
180
181	/* ---------------------------------------------
182	 * Disable the optional ACP.
183	 * ---------------------------------------------
184	 */
185	bl	plat_disable_acp
186
187	/* ---------------------------------------------
188	 * Flush L2 caches.
189	 * ---------------------------------------------
190	 */
191	mov	x0, #DCCISW
192	bl	dcsw_op_level2
193
194	/* ---------------------------------------------
195	 * Come out of intra cluster coherency
196	 * ---------------------------------------------
197	 */
198	mov	x30, x18
199	b	cortex_a73_disable_smp
200endfunc cortex_a73_cluster_pwr_dwn
201
202func check_errata_cve_2017_5715
203	cpu_check_csv2	x0, 1f
204#if WORKAROUND_CVE_2017_5715
205	mov	x0, #ERRATA_APPLIES
206#else
207	mov	x0, #ERRATA_MISSING
208#endif
209	ret
2101:
211	mov	x0, #ERRATA_NOT_APPLIES
212	ret
213endfunc check_errata_cve_2017_5715
214
215func check_errata_cve_2018_3639
216#if WORKAROUND_CVE_2018_3639
217	mov	x0, #ERRATA_APPLIES
218#else
219	mov	x0, #ERRATA_MISSING
220#endif
221	ret
222endfunc check_errata_cve_2018_3639
223
224#if REPORT_ERRATA
225/*
226 * Errata printing function for Cortex A75. Must follow AAPCS.
227 */
228func cortex_a73_errata_report
229	stp	x8, x30, [sp, #-16]!
230
231	bl	cpu_get_rev_var
232	mov	x8, x0
233
234	/*
235	 * Report all errata. The revision-variant information is passed to
236	 * checking functions of each errata.
237	 */
238	report_errata ERRATA_A73_852427, cortex_a73, 852427
239	report_errata ERRATA_A73_855423, cortex_a73, 855423
240	report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
241	report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
242
243	ldp	x8, x30, [sp], #16
244	ret
245endfunc cortex_a73_errata_report
246#endif
247
248	/* ---------------------------------------------
249	 * This function provides cortex_a73 specific
250	 * register information for crash reporting.
251	 * It needs to return with x6 pointing to
252	 * a list of register names in ascii and
253	 * x8 - x15 having values of registers to be
254	 * reported.
255	 * ---------------------------------------------
256	 */
257.section .rodata.cortex_a73_regs, "aS"
258cortex_a73_regs:  /* The ascii list of register names to be reported */
259	.asciz	"cpuectlr_el1", "l2merrsr_el1", ""
260
261func cortex_a73_cpu_reg_dump
262	adr	x6, cortex_a73_regs
263	mrs	x8, CORTEX_A73_CPUECTLR_EL1
264	mrs	x9, CORTEX_A73_L2MERRSR_EL1
265	ret
266endfunc cortex_a73_cpu_reg_dump
267
268declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
269	cortex_a73_reset_func, \
270	check_errata_cve_2017_5715, \
271	CPU_NO_EXTRA2_FUNC, \
272	cortex_a73_core_pwr_dwn, \
273	cortex_a73_cluster_pwr_dwn
274