1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
9
10 #include <linux/bitops.h>
11 #include <linux/mtd/cfi.h>
12 #include <linux/mtd/mtd.h>
13
14 /*
15 * Manufacturer IDs
16 *
17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
18 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
19 */
20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
21 #define SNOR_MFR_GIGADEVICE 0xc8
22 #define SNOR_MFR_INTEL CFI_MFR_INTEL
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
25 #define SNOR_MFR_ISSI CFI_MFR_PMC
26 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
27 #define SNOR_MFR_SPANSION CFI_MFR_AMD
28 #define SNOR_MFR_SST CFI_MFR_SST
29 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
30
31 /*
32 * Note on opcode nomenclature: some opcodes have a format like
33 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
34 * of I/O lines used for the opcode, address, and data (respectively). The
35 * FUNCTION has an optional suffix of '4', to represent an opcode which
36 * requires a 4-byte (32-bit) address.
37 */
38
39 /* Flash opcodes. */
40 #define SPINOR_OP_WREN 0x06 /* Write enable */
41 #define SPINOR_OP_RDSR 0x05 /* Read status register */
42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
43 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
44 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
45 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
46 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
47 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
48 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
49 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
50 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
51 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
52 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
53 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
54 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
55 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
56 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
57 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
58 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
59 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
60 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
61 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
62 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
63 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
64 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
65 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
66 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
67 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
68 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
69 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
70
71 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
72 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
73 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
74 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
75 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
76 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
77 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
78 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
79 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
80 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
81 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
82 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
83 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
84 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
85 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
86 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
87 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
88
89 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
90 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
91 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
92 #define SPINOR_OP_READ_1_4_4_DTR 0xed
93
94 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
95 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
96 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
97
98 /* Used for SST flashes only. */
99 #define SPINOR_OP_BP 0x02 /* Byte program */
100 #define SPINOR_OP_WRDI 0x04 /* Write disable */
101 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
102
103 /* Used for SST26* flashes only. */
104 #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
105 #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
106
107 /* Used for S3AN flashes only */
108 #define SPINOR_OP_XSE 0x50 /* Sector erase */
109 #define SPINOR_OP_XPP 0x82 /* Page program */
110 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
111
112 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
113 #define XSR_RDY BIT(7) /* Ready */
114
115 /* Used for Macronix and Winbond flashes. */
116 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
117 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
118
119 /* Used for Spansion flashes only. */
120 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
121 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
122 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
123
124 /* Used for Micron flashes only. */
125 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
126 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
127
128 /* Status Register bits. */
129 #define SR_WIP BIT(0) /* Write in progress */
130 #define SR_WEL BIT(1) /* Write enable latch */
131 /* meaning of other SR_* bits may differ between vendors */
132 #define SR_BP0 BIT(2) /* Block protect 0 */
133 #define SR_BP1 BIT(3) /* Block protect 1 */
134 #define SR_BP2 BIT(4) /* Block protect 2 */
135 #define SR_TB BIT(5) /* Top/Bottom protect */
136 #define SR_SRWD BIT(7) /* SR write protect */
137 /* Spansion/Cypress specific status bits */
138 #define SR_E_ERR BIT(5)
139 #define SR_P_ERR BIT(6)
140
141 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
142
143 /* Enhanced Volatile Configuration Register bits */
144 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
145
146 /* Flag Status Register bits */
147 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
148 #define FSR_E_ERR BIT(5) /* Erase operation status */
149 #define FSR_P_ERR BIT(4) /* Program operation status */
150 #define FSR_PT_ERR BIT(1) /* Protection error bit */
151
152 /* Configuration Register bits. */
153 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
154
155 /* Status Register 2 bits. */
156 #define SR2_QUAD_EN_BIT7 BIT(7)
157
158 /* Supported SPI protocols */
159 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
160 #define SNOR_PROTO_INST_SHIFT 16
161 #define SNOR_PROTO_INST(_nbits) \
162 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
163 SNOR_PROTO_INST_MASK)
164
165 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
166 #define SNOR_PROTO_ADDR_SHIFT 8
167 #define SNOR_PROTO_ADDR(_nbits) \
168 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
169 SNOR_PROTO_ADDR_MASK)
170
171 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
172 #define SNOR_PROTO_DATA_SHIFT 0
173 #define SNOR_PROTO_DATA(_nbits) \
174 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
175 SNOR_PROTO_DATA_MASK)
176
177 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
178
179 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
180 (SNOR_PROTO_INST(_inst_nbits) | \
181 SNOR_PROTO_ADDR(_addr_nbits) | \
182 SNOR_PROTO_DATA(_data_nbits))
183 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
184 (SNOR_PROTO_IS_DTR | \
185 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
186
187 enum spi_nor_protocol {
188 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
189 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
190 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
191 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
192 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
193 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
194 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
195 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
196 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
197 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
198
199 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
200 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
201 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
202 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
203 };
204
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)205 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
206 {
207 return !!(proto & SNOR_PROTO_IS_DTR);
208 }
209
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)210 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
211 {
212 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
213 SNOR_PROTO_INST_SHIFT;
214 }
215
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)216 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
217 {
218 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
219 SNOR_PROTO_ADDR_SHIFT;
220 }
221
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)222 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
223 {
224 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
225 SNOR_PROTO_DATA_SHIFT;
226 }
227
spi_nor_get_protocol_width(enum spi_nor_protocol proto)228 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
229 {
230 return spi_nor_get_protocol_data_nbits(proto);
231 }
232
233 #define SPI_NOR_MAX_CMD_SIZE 8
234 enum spi_nor_ops {
235 SPI_NOR_OPS_READ = 0,
236 SPI_NOR_OPS_WRITE,
237 SPI_NOR_OPS_ERASE,
238 SPI_NOR_OPS_LOCK,
239 SPI_NOR_OPS_UNLOCK,
240 };
241
242 enum spi_nor_option_flags {
243 SNOR_F_USE_FSR = BIT(0),
244 SNOR_F_HAS_SR_TB = BIT(1),
245 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
246 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
247 SNOR_F_READY_XSR_RDY = BIT(4),
248 SNOR_F_USE_CLSR = BIT(5),
249 SNOR_F_BROKEN_RESET = BIT(6),
250 };
251
252 /**
253 * struct flash_info - Forward declaration of a structure used internally by
254 * spi_nor_scan()
255 */
256 struct flash_info;
257
258 /*
259 * TODO: Remove, once all users of spi_flash interface are moved to MTD
260 *
261 struct spi_flash {
262 * Defined below (keep this text to enable searching for spi_flash decl)
263 * }
264 */
265 #ifndef DT_PLAT_C
266 #define spi_flash spi_nor
267 #endif
268
269 /**
270 * struct spi_nor - Structure for defining a the SPI NOR layer
271 * @mtd: point to a mtd_info structure
272 * @lock: the lock for the read/write/erase/lock/unlock operations
273 * @dev: point to a spi device, or a spi nor controller device.
274 * @info: spi-nor part JDEC MFR id and other info
275 * @manufacturer_sfdp: manufacturer specific SFDP table
276 * @page_size: the page size of the SPI NOR
277 * @addr_width: number of address bytes
278 * @erase_opcode: the opcode for erasing a sector
279 * @read_opcode: the read opcode
280 * @read_dummy: the dummy needed by the read operation
281 * @program_opcode: the program opcode
282 * @bank_read_cmd: Bank read cmd
283 * @bank_write_cmd: Bank write cmd
284 * @bank_curr: Current flash bank
285 * @sst_write_second: used by the SST write operation
286 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
287 * @read_proto: the SPI protocol for read operations
288 * @write_proto: the SPI protocol for write operations
289 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
290 * @cmd_buf: used by the write_reg
291 * @prepare: [OPTIONAL] do some preparations for the
292 * read/write/erase/lock/unlock operations
293 * @unprepare: [OPTIONAL] do some post work after the
294 * read/write/erase/lock/unlock operations
295 * @read_reg: [DRIVER-SPECIFIC] read out the register
296 * @write_reg: [DRIVER-SPECIFIC] write data to the register
297 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
298 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
299 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
300 * at the offset @offs; if not provided by the driver,
301 * spi-nor will send the erase opcode via write_reg()
302 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
303 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
304 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
305 * completely locked
306 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
307 * @priv: the private data
308 */
309 struct spi_nor {
310 struct mtd_info mtd;
311 struct udevice *dev;
312 struct spi_slave *spi;
313 const struct flash_info *info;
314 u8 *manufacturer_sfdp;
315 u32 page_size;
316 u8 addr_width;
317 u8 erase_opcode;
318 u8 read_opcode;
319 u8 read_dummy;
320 u8 program_opcode;
321 #ifdef CONFIG_SPI_FLASH_BAR
322 u8 bank_read_cmd;
323 u8 bank_write_cmd;
324 u8 bank_curr;
325 #endif
326 enum spi_nor_protocol read_proto;
327 enum spi_nor_protocol write_proto;
328 enum spi_nor_protocol reg_proto;
329 bool sst_write_second;
330 u32 flags;
331 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
332
333 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
334 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
335 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
336 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
337
338 ssize_t (*read)(struct spi_nor *nor, loff_t from,
339 size_t len, u_char *read_buf);
340 ssize_t (*write)(struct spi_nor *nor, loff_t to,
341 size_t len, const u_char *write_buf);
342 int (*erase)(struct spi_nor *nor, loff_t offs);
343
344 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
345 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
346 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
347 int (*quad_enable)(struct spi_nor *nor);
348
349 void *priv;
350 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
351 const char *name;
352 u32 size;
353 u32 sector_size;
354 u32 erase_size;
355 };
356
357 #ifndef __UBOOT__
spi_nor_set_flash_node(struct spi_nor * nor,const struct device_node * np)358 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
359 const struct device_node *np)
360 {
361 mtd_set_of_node(&nor->mtd, np);
362 }
363
364 static inline const struct
spi_nor_get_flash_node(struct spi_nor * nor)365 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
366 {
367 return mtd_get_of_node(&nor->mtd);
368 }
369 #endif /* __UBOOT__ */
370
371 /**
372 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
373 * supported by the SPI controller (bus master).
374 * @mask: the bitmask listing all the supported hw capabilies
375 */
376 struct spi_nor_hwcaps {
377 u32 mask;
378 };
379
380 /*
381 *(Fast) Read capabilities.
382 * MUST be ordered by priority: the higher bit position, the higher priority.
383 * As a matter of performances, it is relevant to use Octo SPI protocols first,
384 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
385 * (Slow) Read.
386 */
387 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
388 #define SNOR_HWCAPS_READ BIT(0)
389 #define SNOR_HWCAPS_READ_FAST BIT(1)
390 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
391
392 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
393 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
394 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
395 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
396 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
397
398 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
399 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
400 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
401 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
402 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
403
404 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
405 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
406 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
407 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
408 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
409
410 /*
411 * Page Program capabilities.
412 * MUST be ordered by priority: the higher bit position, the higher priority.
413 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
414 * legacy SPI 1-1-1 protocol.
415 * Note that Dual Page Programs are not supported because there is no existing
416 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
417 * implements such commands.
418 */
419 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
420 #define SNOR_HWCAPS_PP BIT(16)
421
422 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
423 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
424 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
425 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
426
427 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
428 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
429 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
430 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
431
432 /**
433 * spi_nor_scan() - scan the SPI NOR
434 * @nor: the spi_nor structure
435 *
436 * The drivers can use this function to scan the SPI NOR.
437 * In the scanning, it will try to get all the necessary information to
438 * fill the mtd_info{} and the spi_nor{}.
439 *
440 * Return: 0 for success, others for failure.
441 */
442 int spi_nor_scan(struct spi_nor *nor);
443
444 #endif
445