1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #ifndef __MSM_DRV_H__
9 #define __MSM_DRV_H__
10
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/cpufreq.h>
14 #include <linux/module.h>
15 #include <linux/component.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/list.h>
21 #include <linux/iommu.h>
22 #include <linux/types.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_device.h>
25 #include <linux/sizes.h>
26 #include <linux/kthread.h>
27
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/drm_fb_helper.h>
33 #include <drm/msm_drm.h>
34 #include <drm/drm_gem.h>
35
36 struct msm_kms;
37 struct msm_gpu;
38 struct msm_mmu;
39 struct msm_mdss;
40 struct msm_rd_state;
41 struct msm_perf_state;
42 struct msm_gem_submit;
43 struct msm_fence_context;
44 struct msm_gem_address_space;
45 struct msm_gem_vma;
46 struct msm_disp_state;
47
48 #define MAX_CRTCS 8
49 #define MAX_PLANES 20
50 #define MAX_ENCODERS 8
51 #define MAX_BRIDGES 8
52 #define MAX_CONNECTORS 8
53
54 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
55
56 enum msm_mdp_plane_property {
57 PLANE_PROP_ZPOS,
58 PLANE_PROP_ALPHA,
59 PLANE_PROP_PREMULTIPLIED,
60 PLANE_PROP_MAX_NUM
61 };
62
63 enum msm_dp_controller {
64 MSM_DP_CONTROLLER_0,
65 MSM_DP_CONTROLLER_1,
66 MSM_DP_CONTROLLER_2,
67 MSM_DP_CONTROLLER_COUNT,
68 };
69
70 #define MSM_GPU_MAX_RINGS 4
71 #define MAX_H_TILES_PER_DISPLAY 2
72
73 /**
74 * enum msm_display_caps - features/capabilities supported by displays
75 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
76 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
77 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
78 * @MSM_DISPLAY_CAP_EDID: EDID supported
79 */
80 enum msm_display_caps {
81 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
82 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
83 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
84 MSM_DISPLAY_CAP_EDID = BIT(3),
85 };
86
87 /**
88 * enum msm_event_wait - type of HW events to wait for
89 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
90 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
91 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
92 */
93 enum msm_event_wait {
94 MSM_ENC_COMMIT_DONE = 0,
95 MSM_ENC_TX_COMPLETE,
96 MSM_ENC_VBLANK,
97 };
98
99 /**
100 * struct msm_display_topology - defines a display topology pipeline
101 * @num_lm: number of layer mixers used
102 * @num_enc: number of compression encoder blocks used
103 * @num_intf: number of interfaces the panel is mounted on
104 */
105 struct msm_display_topology {
106 u32 num_lm;
107 u32 num_enc;
108 u32 num_intf;
109 u32 num_dspp;
110 };
111
112 /**
113 * struct msm_display_info - defines display properties
114 * @intf_type: DRM_MODE_ENCODER_ type
115 * @capabilities: Bitmask of display flags
116 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
117 * @h_tile_instance: Controller instance used per tile. Number of elements is
118 * based on num_of_h_tiles
119 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
120 * used instead of panel TE in cmd mode panels
121 */
122 struct msm_display_info {
123 int intf_type;
124 uint32_t capabilities;
125 uint32_t num_of_h_tiles;
126 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
127 bool is_te_using_watchdog_timer;
128 };
129
130 /* Commit/Event thread specific structure */
131 struct msm_drm_thread {
132 struct drm_device *dev;
133 unsigned int crtc_id;
134 struct kthread_worker *worker;
135 };
136
137 struct msm_drm_private {
138
139 struct drm_device *dev;
140
141 struct msm_kms *kms;
142
143 /* subordinate devices, if present: */
144 struct platform_device *gpu_pdev;
145
146 /* top level MDSS wrapper device (for MDP5/DPU only) */
147 struct msm_mdss *mdss;
148
149 /* possibly this should be in the kms component, but it is
150 * shared by both mdp4 and mdp5..
151 */
152 struct hdmi *hdmi;
153
154 /* eDP is for mdp5 only, but kms has not been created
155 * when edp_bind() and edp_init() are called. Here is the only
156 * place to keep the edp instance.
157 */
158 struct msm_edp *edp;
159
160 /* DSI is shared by mdp4 and mdp5 */
161 struct msm_dsi *dsi[2];
162
163 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
164
165 /* when we have more than one 'msm_gpu' these need to be an array: */
166 struct msm_gpu *gpu;
167 struct msm_file_private *lastctx;
168 /* gpu is only set on open(), but we need this info earlier */
169 bool is_a2xx;
170 bool has_cached_coherent;
171
172 struct drm_fb_helper *fbdev;
173
174 struct msm_rd_state *rd; /* debugfs to dump all submits */
175 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
176 struct msm_perf_state *perf;
177
178 /**
179 * List of all GEM objects (mainly for debugfs, protected by obj_lock
180 * (acquire before per GEM object lock)
181 */
182 struct list_head objects;
183 struct mutex obj_lock;
184
185 /**
186 * LRUs of inactive GEM objects. Every bo is either in one of the
187 * inactive lists (depending on whether or not it is shrinkable) or
188 * gpu->active_list (for the gpu it is active on[1]), or transiently
189 * on a temporary list as the shrinker is running.
190 *
191 * Note that inactive_willneed also contains pinned and vmap'd bos,
192 * but the number of pinned-but-not-active objects is small (scanout
193 * buffers, ringbuffer, etc).
194 *
195 * These lists are protected by mm_lock (which should be acquired
196 * before per GEM object lock). One should *not* hold mm_lock in
197 * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
198 *
199 * [1] if someone ever added support for the old 2d cores, there could be
200 * more than one gpu object
201 */
202 struct list_head inactive_willneed; /* inactive + potentially unpin/evictable */
203 struct list_head inactive_dontneed; /* inactive + shrinkable */
204 struct list_head inactive_unpinned; /* inactive + purged or unpinned */
205 long shrinkable_count; /* write access under mm_lock */
206 long evictable_count; /* write access under mm_lock */
207 struct mutex mm_lock;
208
209 struct workqueue_struct *wq;
210
211 unsigned int num_planes;
212 struct drm_plane *planes[MAX_PLANES];
213
214 unsigned int num_crtcs;
215 struct drm_crtc *crtcs[MAX_CRTCS];
216
217 struct msm_drm_thread event_thread[MAX_CRTCS];
218
219 unsigned int num_encoders;
220 struct drm_encoder *encoders[MAX_ENCODERS];
221
222 unsigned int num_bridges;
223 struct drm_bridge *bridges[MAX_BRIDGES];
224
225 unsigned int num_connectors;
226 struct drm_connector *connectors[MAX_CONNECTORS];
227
228 /* Properties */
229 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
230
231 /* VRAM carveout, used when no IOMMU: */
232 struct {
233 unsigned long size;
234 dma_addr_t paddr;
235 /* NOTE: mm managed at the page level, size is in # of pages
236 * and position mm_node->start is in # of pages:
237 */
238 struct drm_mm mm;
239 spinlock_t lock; /* Protects drm_mm node allocation/removal */
240 } vram;
241
242 struct notifier_block vmap_notifier;
243 struct shrinker shrinker;
244
245 struct drm_atomic_state *pm_state;
246
247 /* For hang detection, in ms */
248 unsigned int hangcheck_period;
249 };
250
251 struct msm_format {
252 uint32_t pixel_format;
253 };
254
255 struct msm_pending_timer;
256
257 int msm_atomic_prepare_fb(struct drm_plane *plane,
258 struct drm_plane_state *new_state);
259 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
260 struct msm_kms *kms, int crtc_idx);
261 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
262 void msm_atomic_commit_tail(struct drm_atomic_state *state);
263 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
264 void msm_atomic_state_clear(struct drm_atomic_state *state);
265 void msm_atomic_state_free(struct drm_atomic_state *state);
266
267 int msm_crtc_enable_vblank(struct drm_crtc *crtc);
268 void msm_crtc_disable_vblank(struct drm_crtc *crtc);
269
270 int msm_gem_init_vma(struct msm_gem_address_space *aspace,
271 struct msm_gem_vma *vma, int npages,
272 u64 range_start, u64 range_end);
273 void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
274 struct msm_gem_vma *vma);
275 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
276 struct msm_gem_vma *vma);
277 int msm_gem_map_vma(struct msm_gem_address_space *aspace,
278 struct msm_gem_vma *vma, int prot,
279 struct sg_table *sgt, int npages);
280 void msm_gem_close_vma(struct msm_gem_address_space *aspace,
281 struct msm_gem_vma *vma);
282
283
284 struct msm_gem_address_space *
285 msm_gem_address_space_get(struct msm_gem_address_space *aspace);
286
287 void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
288
289 struct msm_gem_address_space *
290 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
291 u64 va_start, u64 size);
292
293 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
294 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
295
296 bool msm_use_mmu(struct drm_device *dev);
297
298 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
299 struct drm_file *file);
300
301 #ifdef CONFIG_DEBUG_FS
302 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
303 #endif
304
305 void msm_gem_shrinker_init(struct drm_device *dev);
306 void msm_gem_shrinker_cleanup(struct drm_device *dev);
307
308 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
309 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
310 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
311 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
312 struct dma_buf_attachment *attach, struct sg_table *sg);
313 int msm_gem_prime_pin(struct drm_gem_object *obj);
314 void msm_gem_prime_unpin(struct drm_gem_object *obj);
315
316 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
317 struct msm_gem_address_space *aspace);
318 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
319 struct msm_gem_address_space *aspace);
320 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
321 struct msm_gem_address_space *aspace, int plane);
322 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
323 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
324 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
325 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
326 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
327 int w, int h, int p, uint32_t format);
328
329 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
330 void msm_fbdev_free(struct drm_device *dev);
331
332 struct hdmi;
333 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
334 struct drm_encoder *encoder);
335 void __init msm_hdmi_register(void);
336 void __exit msm_hdmi_unregister(void);
337
338 struct msm_edp;
339 void __init msm_edp_register(void);
340 void __exit msm_edp_unregister(void);
341 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
342 struct drm_encoder *encoder);
343
344 struct msm_dsi;
345 #ifdef CONFIG_DRM_MSM_DSI
346 void __init msm_dsi_register(void);
347 void __exit msm_dsi_unregister(void);
348 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
349 struct drm_encoder *encoder);
350 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
351 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
352 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
353 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
354 #else
msm_dsi_register(void)355 static inline void __init msm_dsi_register(void)
356 {
357 }
msm_dsi_unregister(void)358 static inline void __exit msm_dsi_unregister(void)
359 {
360 }
msm_dsi_modeset_init(struct msm_dsi * msm_dsi,struct drm_device * dev,struct drm_encoder * encoder)361 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
362 struct drm_device *dev,
363 struct drm_encoder *encoder)
364 {
365 return -EINVAL;
366 }
msm_dsi_snapshot(struct msm_disp_state * disp_state,struct msm_dsi * msm_dsi)367 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
368 {
369 }
msm_dsi_is_cmd_mode(struct msm_dsi * msm_dsi)370 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
371 {
372 return false;
373 }
msm_dsi_is_bonded_dsi(struct msm_dsi * msm_dsi)374 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
375 {
376 return false;
377 }
msm_dsi_is_master_dsi(struct msm_dsi * msm_dsi)378 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
379 {
380 return false;
381 }
382 #endif
383
384 #ifdef CONFIG_DRM_MSM_DP
385 int __init msm_dp_register(void);
386 void __exit msm_dp_unregister(void);
387 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
388 struct drm_encoder *encoder);
389 int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder);
390 int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder);
391 int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder);
392 void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder,
393 struct drm_display_mode *mode,
394 struct drm_display_mode *adjusted_mode);
395 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
396 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
397
398 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
399
400 #else
msm_dp_register(void)401 static inline int __init msm_dp_register(void)
402 {
403 return -EINVAL;
404 }
msm_dp_unregister(void)405 static inline void __exit msm_dp_unregister(void)
406 {
407 }
msm_dp_modeset_init(struct msm_dp * dp_display,struct drm_device * dev,struct drm_encoder * encoder)408 static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
409 struct drm_device *dev,
410 struct drm_encoder *encoder)
411 {
412 return -EINVAL;
413 }
msm_dp_display_enable(struct msm_dp * dp,struct drm_encoder * encoder)414 static inline int msm_dp_display_enable(struct msm_dp *dp,
415 struct drm_encoder *encoder)
416 {
417 return -EINVAL;
418 }
msm_dp_display_disable(struct msm_dp * dp,struct drm_encoder * encoder)419 static inline int msm_dp_display_disable(struct msm_dp *dp,
420 struct drm_encoder *encoder)
421 {
422 return -EINVAL;
423 }
msm_dp_display_pre_disable(struct msm_dp * dp,struct drm_encoder * encoder)424 static inline int msm_dp_display_pre_disable(struct msm_dp *dp,
425 struct drm_encoder *encoder)
426 {
427 return -EINVAL;
428 }
msm_dp_display_mode_set(struct msm_dp * dp,struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)429 static inline void msm_dp_display_mode_set(struct msm_dp *dp,
430 struct drm_encoder *encoder,
431 struct drm_display_mode *mode,
432 struct drm_display_mode *adjusted_mode)
433 {
434 }
435
msm_dp_irq_postinstall(struct msm_dp * dp_display)436 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
437 {
438 }
439
msm_dp_snapshot(struct msm_disp_state * disp_state,struct msm_dp * dp_display)440 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
441 {
442 }
443
msm_dp_debugfs_init(struct msm_dp * dp_display,struct drm_minor * minor)444 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
445 struct drm_minor *minor)
446 {
447 }
448
449 #endif
450
451 void __init msm_mdp_register(void);
452 void __exit msm_mdp_unregister(void);
453 void __init msm_dpu_register(void);
454 void __exit msm_dpu_unregister(void);
455
456 #ifdef CONFIG_DEBUG_FS
457 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
458 int msm_debugfs_late_init(struct drm_device *dev);
459 int msm_rd_debugfs_init(struct drm_minor *minor);
460 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
461 __printf(3, 4)
462 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
463 const char *fmt, ...);
464 int msm_perf_debugfs_init(struct drm_minor *minor);
465 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
466 #else
msm_debugfs_late_init(struct drm_device * dev)467 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
468 __printf(3, 4)
msm_rd_dump_submit(struct msm_rd_state * rd,struct msm_gem_submit * submit,const char * fmt,...)469 static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
470 struct msm_gem_submit *submit,
471 const char *fmt, ...) {}
msm_rd_debugfs_cleanup(struct msm_drm_private * priv)472 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
msm_perf_debugfs_cleanup(struct msm_drm_private * priv)473 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
474 #endif
475
476 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
477
478 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
479 const char *name);
480 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
481 const char *dbgname);
482 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
483 const char *dbgname, phys_addr_t *size);
484 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
485 const char *dbgname);
486 void msm_writel(u32 data, void __iomem *addr);
487 u32 msm_readl(const void __iomem *addr);
488 void msm_rmw(void __iomem *addr, u32 mask, u32 or);
489
490 /**
491 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
492 *
493 * @timer: hrtimer to control when the kthread work is triggered
494 * @work: the kthread work
495 * @worker: the kthread worker the work will be scheduled on
496 */
497 struct msm_hrtimer_work {
498 struct hrtimer timer;
499 struct kthread_work work;
500 struct kthread_worker *worker;
501 };
502
503 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
504 ktime_t wakeup_time,
505 enum hrtimer_mode mode);
506 void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
507 struct kthread_worker *worker,
508 kthread_work_func_t fn,
509 clockid_t clock_id,
510 enum hrtimer_mode mode);
511
512 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
513 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
514
align_pitch(int width,int bpp)515 static inline int align_pitch(int width, int bpp)
516 {
517 int bytespp = (bpp + 7) / 8;
518 /* adreno needs pitch aligned to 32 pixels: */
519 return bytespp * ALIGN(width, 32);
520 }
521
522 /* for the generated headers: */
523 #define INVALID_IDX(idx) ({BUG(); 0;})
524 #define fui(x) ({BUG(); 0;})
525 #define _mesa_float_to_half(x) ({BUG(); 0;})
526
527
528 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
529
530 /* for conditionally setting boolean flag(s): */
531 #define COND(bool, val) ((bool) ? (val) : 0)
532
timeout_to_jiffies(const ktime_t * timeout)533 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
534 {
535 ktime_t now = ktime_get();
536 s64 remaining_jiffies;
537
538 if (ktime_compare(*timeout, now) < 0) {
539 remaining_jiffies = 0;
540 } else {
541 ktime_t rem = ktime_sub(*timeout, now);
542 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
543 }
544
545 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX);
546 }
547
548 #endif /* __MSM_DRV_H__ */
549