1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2#include <dt-bindings/interrupt-controller/mips-gic.h>
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/clock/mt7621-clk.h>
5
6/ {
7	#address-cells = <1>;
8	#size-cells = <1>;
9	compatible = "mediatek,mt7621-soc";
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "mips,mips1004Kc";
18			reg = <0>;
19		};
20
21		cpu@1 {
22			device_type = "cpu";
23			compatible = "mips,mips1004Kc";
24			reg = <1>;
25		};
26	};
27
28	cpuintc: cpuintc@0 {
29		#address-cells = <0>;
30		#interrupt-cells = <1>;
31		interrupt-controller;
32		compatible = "mti,cpu-interrupt-controller";
33	};
34
35	aliases {
36		serial0 = &uartlite;
37	};
38
39
40	mmc_fixed_3v3: fixedregulator@0 {
41		compatible = "regulator-fixed";
42		regulator-name = "mmc_power";
43		regulator-min-microvolt = <3300000>;
44		regulator-max-microvolt = <3300000>;
45		enable-active-high;
46		regulator-always-on;
47	  };
48
49	  mmc_fixed_1v8_io: fixedregulator@1 {
50		compatible = "regulator-fixed";
51		regulator-name = "mmc_io";
52		regulator-min-microvolt = <1800000>;
53		regulator-max-microvolt = <1800000>;
54		enable-active-high;
55		regulator-always-on;
56	};
57
58	palmbus: palmbus@1e000000 {
59		compatible = "palmbus";
60		reg = <0x1e000000 0x100000>;
61		ranges = <0x0 0x1e000000 0x0fffff>;
62
63		#address-cells = <1>;
64		#size-cells = <1>;
65
66		sysc: syscon@0 {
67			compatible = "mediatek,mt7621-sysc", "syscon";
68			reg = <0x0 0x100>;
69			#clock-cells = <1>;
70			ralink,memctl = <&memc>;
71			clock-output-names = "xtal", "cpu", "bus",
72					     "50m", "125m", "150m",
73					     "250m", "270m";
74		};
75
76		wdt: wdt@100 {
77			compatible = "mediatek,mt7621-wdt";
78			reg = <0x100 0x100>;
79		};
80
81		gpio: gpio@600 {
82			#gpio-cells = <2>;
83			#interrupt-cells = <2>;
84			compatible = "mediatek,mt7621-gpio";
85			gpio-controller;
86			gpio-ranges = <&pinctrl 0 0 95>;
87			interrupt-controller;
88			reg = <0x600 0x100>;
89			interrupt-parent = <&gic>;
90			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
91		};
92
93		i2c: i2c@900 {
94			compatible = "mediatek,mt7621-i2c";
95			reg = <0x900 0x100>;
96
97			clocks = <&sysc MT7621_CLK_I2C>;
98			clock-names = "i2c";
99			resets = <&rstctrl 16>;
100			reset-names = "i2c";
101
102			#address-cells = <1>;
103			#size-cells = <0>;
104
105			status = "disabled";
106
107			pinctrl-names = "default";
108			pinctrl-0 = <&i2c_pins>;
109		};
110
111		memc: syscon@5000 {
112			compatible = "mediatek,mt7621-memc", "syscon";
113			reg = <0x5000 0x1000>;
114		};
115
116		uartlite: uartlite@c00 {
117			compatible = "ns16550a";
118			reg = <0xc00 0x100>;
119
120			clocks = <&sysc MT7621_CLK_UART1>;
121			clock-names = "uart1";
122
123			interrupt-parent = <&gic>;
124			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
125
126			reg-shift = <2>;
127			reg-io-width = <4>;
128			no-loopback-test;
129		};
130
131		spi0: spi@b00 {
132			status = "disabled";
133
134			compatible = "ralink,mt7621-spi";
135			reg = <0xb00 0x100>;
136
137			clocks = <&sysc MT7621_CLK_SPI>;
138			clock-names = "spi";
139
140			resets = <&rstctrl 18>;
141			reset-names = "spi";
142
143			#address-cells = <1>;
144			#size-cells = <0>;
145
146			pinctrl-names = "default";
147			pinctrl-0 = <&spi_pins>;
148		};
149
150		gdma: gdma@2800 {
151			compatible = "ralink,rt3883-gdma";
152			reg = <0x2800 0x800>;
153
154			clocks = <&sysc MT7621_CLK_GDMA>;
155			clock-names = "gdma";
156			resets = <&rstctrl 14>;
157			reset-names = "dma";
158
159			interrupt-parent = <&gic>;
160			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
161
162			#dma-cells = <1>;
163			#dma-channels = <16>;
164			#dma-requests = <16>;
165
166			status = "disabled";
167		};
168
169		hsdma: hsdma@7000 {
170			compatible = "mediatek,mt7621-hsdma";
171			reg = <0x7000 0x1000>;
172
173			clocks = <&sysc MT7621_CLK_HSDMA>;
174			clock-names = "hsdma";
175			resets = <&rstctrl 5>;
176			reset-names = "hsdma";
177
178			interrupt-parent = <&gic>;
179			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
180
181			#dma-cells = <1>;
182			#dma-channels = <1>;
183			#dma-requests = <1>;
184
185			status = "disabled";
186		};
187	};
188
189	pinctrl: pinctrl {
190		compatible = "ralink,rt2880-pinmux";
191
192		i2c_pins: i2c0-pins {
193			pinmux {
194				groups = "i2c";
195				function = "i2c";
196			};
197		};
198
199		spi_pins: spi0-pins {
200			pinmux {
201				groups = "spi";
202				function = "spi";
203			};
204		};
205
206		uart1_pins: uart1-pins {
207			pinmux {
208				groups = "uart1";
209				function = "uart1";
210			};
211		};
212
213		uart2_pins: uart2-pins {
214			pinmux {
215				groups = "uart2";
216				function = "uart2";
217			};
218		};
219
220		uart3_pins: uart3-pins {
221			pinmux {
222				groups = "uart3";
223				function = "uart3";
224			};
225		};
226
227		rgmii1_pins: rgmii1-pins {
228			pinmux {
229				groups = "rgmii1";
230				function = "rgmii1";
231			};
232		};
233
234		rgmii2_pins: rgmii2-pins {
235			pinmux {
236				groups = "rgmii2";
237				function = "rgmii2";
238			};
239		};
240
241		mdio_pins: mdio0-pins {
242			pinmux {
243				groups = "mdio";
244				function = "mdio";
245			};
246		};
247
248		pcie_pins: pcie0-pins {
249			pinmux {
250				groups = "pcie";
251				function = "gpio";
252			};
253		};
254
255		nand_pins: nand0-pins {
256			spi-pinmux {
257				groups = "spi";
258				function = "nand1";
259			};
260
261			sdhci-pinmux {
262				groups = "sdhci";
263				function = "nand2";
264			};
265		};
266
267		sdhci_pins: sdhci0-pins {
268			pinmux {
269				groups = "sdhci";
270				function = "sdhci";
271			};
272		};
273	};
274
275	rstctrl: rstctrl {
276		compatible = "ralink,rt2880-reset";
277		#reset-cells = <1>;
278	};
279
280	sdhci: sdhci@1e130000 {
281		status = "disabled";
282
283		compatible = "mediatek,mt7620-mmc";
284		reg = <0x1e130000 0x4000>;
285
286		bus-width = <4>;
287		max-frequency = <48000000>;
288		cap-sd-highspeed;
289		cap-mmc-highspeed;
290		vmmc-supply = <&mmc_fixed_3v3>;
291		vqmmc-supply = <&mmc_fixed_1v8_io>;
292		disable-wp;
293
294		pinctrl-names = "default", "state_uhs";
295		pinctrl-0 = <&sdhci_pins>;
296		pinctrl-1 = <&sdhci_pins>;
297
298		clocks = <&sysc MT7621_CLK_SHXC>,
299			 <&sysc MT7621_CLK_50M>;
300		clock-names = "source", "hclk";
301
302		interrupt-parent = <&gic>;
303		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
304	};
305
306	xhci: xhci@1e1c0000 {
307		status = "okay";
308
309		compatible = "mediatek,mt8173-xhci";
310		reg = <0x1e1c0000 0x1000
311		       0x1e1d0700 0x0100>;
312		reg-names = "mac", "ippc";
313
314		clocks = <&sysc MT7621_CLK_XTAL>;
315		clock-names = "sys_ck";
316
317		interrupt-parent = <&gic>;
318		interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
319	};
320
321	gic: interrupt-controller@1fbc0000 {
322		compatible = "mti,gic";
323		reg = <0x1fbc0000 0x2000>;
324
325		interrupt-controller;
326		#interrupt-cells = <3>;
327
328		mti,reserved-cpu-vectors = <7>;
329
330		timer {
331			compatible = "mti,gic-timer";
332			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
333			clocks = <&sysc MT7621_CLK_CPU>;
334		};
335	};
336
337	cpc: cpc@1fbf0000 {
338		compatible = "mti,mips-cpc";
339		reg = <0x1fbf0000 0x8000>;
340	};
341
342	cdmm: cdmm@1fbf8000 {
343		compatible = "mti,mips-cdmm";
344		reg = <0x1fbf8000 0x8000>;
345	};
346
347	ethernet: ethernet@1e100000 {
348		compatible = "mediatek,mt7621-eth";
349		reg = <0x1e100000 0x10000>;
350
351		clocks = <&sysc MT7621_CLK_FE>,
352			 <&sysc MT7621_CLK_ETH>;
353		clock-names = "fe", "ethif";
354
355		#address-cells = <1>;
356		#size-cells = <0>;
357
358		resets = <&rstctrl 6 &rstctrl 23>;
359		reset-names = "fe", "eth";
360
361		interrupt-parent = <&gic>;
362		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
363
364		mediatek,ethsys = <&sysc>;
365
366
367		gmac0: mac@0 {
368			compatible = "mediatek,eth-mac";
369			reg = <0>;
370			phy-mode = "rgmii";
371			fixed-link {
372				speed = <1000>;
373				full-duplex;
374				pause;
375			};
376		};
377		gmac1: mac@1 {
378			compatible = "mediatek,eth-mac";
379			reg = <1>;
380			status = "off";
381			phy-mode = "rgmii-rxid";
382			phy-handle = <&phy_external>;
383		};
384		mdio-bus {
385			#address-cells = <1>;
386			#size-cells = <0>;
387
388			phy_external: ethernet-phy@5 {
389				status = "off";
390				reg = <5>;
391				phy-mode = "rgmii-rxid";
392
393				pinctrl-names = "default";
394				pinctrl-0 = <&rgmii2_pins>;
395			};
396
397			switch0: switch0@0 {
398				compatible = "mediatek,mt7621";
399				#address-cells = <1>;
400				#size-cells = <0>;
401				reg = <0>;
402				mediatek,mcm;
403				resets = <&rstctrl 2>;
404				reset-names = "mcm";
405				interrupt-controller;
406				#interrupt-cells = <1>;
407				interrupt-parent = <&gic>;
408				interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
409
410				ports {
411					#address-cells = <1>;
412					#size-cells = <0>;
413					reg = <0>;
414					port@0 {
415						status = "off";
416						reg = <0>;
417						label = "lan0";
418					};
419					port@1 {
420						status = "off";
421						reg = <1>;
422						label = "lan1";
423					};
424					port@2 {
425						status = "off";
426						reg = <2>;
427						label = "lan2";
428					};
429					port@3 {
430						status = "off";
431						reg = <3>;
432						label = "lan3";
433					};
434					port@4 {
435						status = "off";
436						reg = <4>;
437						label = "lan4";
438					};
439					port@6 {
440						reg = <6>;
441						label = "cpu";
442						ethernet = <&gmac0>;
443						phy-mode = "trgmii";
444						fixed-link {
445							speed = <1000>;
446							full-duplex;
447						};
448					};
449				};
450			};
451		};
452	};
453
454	pcie: pcie@1e140000 {
455		compatible = "mediatek,mt7621-pci";
456		reg = <0x1e140000 0x100>, /* host-pci bridge registers */
457		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */
458		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */
459		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */
460		#address-cells = <3>;
461		#size-cells = <2>;
462
463		pinctrl-names = "default";
464		pinctrl-0 = <&pcie_pins>;
465
466		device_type = "pci";
467
468		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
469			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
470
471		#interrupt-cells = <1>;
472		interrupt-map-mask = <0xF800 0 0 0>;
473		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
474				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
475				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
476
477		status = "disabled";
478
479		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
480
481		pcie@0,0 {
482			reg = <0x0000 0 0 0 0>;
483			#address-cells = <3>;
484			#size-cells = <2>;
485			device_type = "pci";
486			#interrupt-cells = <1>;
487			interrupt-map-mask = <0 0 0 0>;
488			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
489			resets = <&rstctrl 24>;
490			clocks = <&sysc MT7621_CLK_PCIE0>;
491			phys = <&pcie0_phy 1>;
492			phy-names = "pcie-phy0";
493			ranges;
494		};
495
496		pcie@1,0 {
497			reg = <0x0800 0 0 0 0>;
498			#address-cells = <3>;
499			#size-cells = <2>;
500			device_type = "pci";
501			#interrupt-cells = <1>;
502			interrupt-map-mask = <0 0 0 0>;
503			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
504			resets = <&rstctrl 25>;
505			clocks = <&sysc MT7621_CLK_PCIE1>;
506			phys = <&pcie0_phy 1>;
507			phy-names = "pcie-phy1";
508			ranges;
509		};
510
511		pcie@2,0 {
512			reg = <0x1000 0 0 0 0>;
513			#address-cells = <3>;
514			#size-cells = <2>;
515			device_type = "pci";
516			#interrupt-cells = <1>;
517			interrupt-map-mask = <0 0 0 0>;
518			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
519			resets = <&rstctrl 26>;
520			clocks = <&sysc MT7621_CLK_PCIE2>;
521			phys = <&pcie2_phy 0>;
522			phy-names = "pcie-phy2";
523			ranges;
524		};
525	};
526
527	pcie0_phy: pcie-phy@1e149000 {
528		compatible = "mediatek,mt7621-pci-phy";
529		reg = <0x1e149000 0x0700>;
530		clocks = <&sysc MT7621_CLK_XTAL>;
531		#phy-cells = <1>;
532	};
533
534	pcie2_phy: pcie-phy@1e14a000 {
535		compatible = "mediatek,mt7621-pci-phy";
536		reg = <0x1e14a000 0x0700>;
537		clocks = <&sysc MT7621_CLK_XTAL>;
538		#phy-cells = <1>;
539	};
540};
541