1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/mt7628-clk.h>
3#include <dt-bindings/reset/mt7628-reset.h>
4
5/ {
6	#address-cells = <1>;
7	#size-cells = <1>;
8	compatible = "ralink,mt7628a-soc";
9
10	cpus {
11		#address-cells = <1>;
12		#size-cells = <0>;
13
14		cpu@0 {
15			compatible = "mti,mips24KEc";
16			device_type = "cpu";
17			reg = <0>;
18		};
19	};
20
21	cpuintc: interrupt-controller {
22		#address-cells = <0>;
23		#interrupt-cells = <1>;
24		interrupt-controller;
25		compatible = "mti,cpu-interrupt-controller";
26	};
27
28	clk48m: clk48m@0 {
29		compatible = "fixed-clock";
30
31		clock-frequency = <48000000>;
32
33		#clock-cells = <0>;
34	};
35
36	palmbus: palmbus@10000000 {
37		compatible = "palmbus", "simple-bus";
38		reg = <0x10000000 0x200000>;
39		ranges = <0x0 0x10000000 0x1FFFFF>;
40
41		#address-cells = <1>;
42		#size-cells = <1>;
43
44		sysc: system-controller@0 {
45			compatible = "ralink,mt7620a-sysc", "syscon";
46			reg = <0x0 0x100>;
47		};
48
49		reboot: resetctl-reboot {
50			compatible = "resetctl-reboot";
51
52			resets = <&rstctrl MT7628_SYS_RST>;
53			reset-names = "sysreset";
54		};
55
56		clkctrl: clkctrl@0x2c {
57			reg = <0x2c 0x8>, <0x10 0x4>;
58			reg-names = "syscfg0", "clkcfg";
59			compatible = "mediatek,mt7628-clk";
60			#clock-cells = <1>;
61			u-boot,dm-pre-reloc;
62		};
63
64		rstctrl: rstctrl@0x34 {
65			reg = <0x34 0x4>;
66			compatible = "mediatek,mtmips-reset";
67			#reset-cells = <1>;
68		};
69
70		pinctrl: pinctrl@60 {
71			compatible = "mediatek,mt7628-pinctrl";
72			reg = <0x3c 0x2c>, <0x1300 0x100>;
73			reg-names = "gpiomode", "padconf";
74
75			pinctrl-names = "default";
76			pinctrl-0 = <&state_default>;
77
78			state_default: pin_state {
79			};
80
81			spi_single_pins: spi_single_pins {
82				groups = "spi";
83				function = "spi";
84			};
85
86			spi_dual_pins: spi_dual_pins {
87				spi_master_pins {
88					groups = "spi";
89					function = "spi";
90				};
91
92				spi_cs1_pin {
93					groups = "spi cs1";
94					function = "spi cs1";
95				};
96			};
97
98			uart0_pins: uart0_pins {
99				groups = "uart0";
100				function = "uart0";
101			};
102
103			uart1_pins: uart1_pins {
104				groups = "uart1";
105				function = "uart1";
106			};
107
108			uart2_pins: uart2_pins {
109				groups = "uart2";
110				function = "uart2";
111			};
112
113			uart2_pwm_pins: uart2_pwm_pins {
114				groups = "spis";
115				function = "pwm_uart2";
116			};
117
118			i2c_pins: i2c_pins {
119				groups = "i2c";
120				function = "i2c";
121			};
122
123			ephy_iot_mode: ephy_iot_mode {
124				ephy4_1_dis {
125					groups = "ephy4_1_pad";
126					function = "digital";
127				};
128
129				ephy0_en {
130					groups = "ephy0";
131					function = "enable";
132				};
133			};
134
135			ephy_router_mode: ephy_router_mode {
136				ephy4_1_en {
137					groups = "ephy4_1_pad";
138					function = "analog";
139				};
140
141				ephy0_en {
142					groups = "ephy0";
143					function = "enable";
144				};
145			};
146
147			sd_iot_mode: sd_iot_mode {
148				ephy4_1_dis {
149					groups = "ephy4_1_pad";
150					function = "digital";
151				};
152
153				sdxc_en {
154					groups = "sdmode";
155					function = "sdxc";
156				};
157
158				sdxc_iot_mode {
159					groups = "sd router";
160					function = "iot";
161				};
162
163				sd_clk_pad {
164					pins = "sd_clk";
165					drive-strength-4g = <8>;
166				};
167			};
168
169			sd_router_mode: sd_router_mode {
170				sdxc_router_mode {
171					groups = "sd router";
172					function = "router";
173				};
174
175				sdxc_map_pins {
176					groups = "gpio0", "i2s", "sdmode", \
177						 "i2c", "uart1";
178					function = "gpio";
179				};
180
181				sd_clk_pad {
182					pins = "gpio0";
183					drive-strength-28 = <8>;
184				};
185			};
186
187			emmc_iot_8bit_mode: emmc_iot_8bit_mode {
188				ephy4_1_dis {
189					groups = "ephy4_1_pad";
190					function = "digital";
191				};
192
193				emmc_en {
194					groups = "sdmode";
195					function = "sdxc";
196				};
197
198				emmc_iot_mode {
199					groups = "sd router";
200					function = "iot";
201				};
202
203				emmc_d4_d5 {
204					groups = "uart2";
205					function = "sdxc d5 d4";
206				};
207
208				emmc_d6 {
209					groups = "pwm1";
210					function = "sdxc d6";
211				};
212
213				emmc_d7 {
214					groups = "pwm0";
215					function = "sdxc d7";
216				};
217
218				sd_clk_pad {
219					pins = "sd_clk";
220					drive-strength-4g = <8>;
221				};
222			};
223		};
224
225		watchdog: watchdog@100 {
226			compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
227			reg = <0x100 0x30>;
228
229			resets = <&rstctrl MT7628_TIMER_RST>;
230			reset-names = "wdt";
231
232			interrupt-parent = <&intc>;
233			interrupts = <24>;
234		};
235
236		intc: interrupt-controller@200 {
237			compatible = "ralink,rt2880-intc";
238			reg = <0x200 0x100>;
239
240			interrupt-controller;
241			#interrupt-cells = <1>;
242
243			resets = <&rstctrl MT7628_INT_RST>;
244			reset-names = "intc";
245
246			interrupt-parent = <&cpuintc>;
247			interrupts = <2>;
248
249			ralink,intc-registers = <0x9c 0xa0
250						 0x6c 0xa4
251						 0x80 0x78>;
252		};
253
254		memory-controller@300 {
255			compatible = "ralink,mt7620a-memc";
256			reg = <0x300 0x100>;
257		};
258
259		gpio@600 {
260			#address-cells = <1>;
261			#size-cells = <0>;
262
263			compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
264			reg = <0x600 0x100>;
265
266			resets = <&rstctrl MT7628_PIO_RST>;
267			reset-names = "pio";
268
269			interrupt-parent = <&intc>;
270			interrupts = <6>;
271
272			gpio0: bank@0 {
273				reg = <0>;
274				compatible = "mtk,mt7621-gpio-bank";
275				gpio-controller;
276				#gpio-cells = <2>;
277			};
278
279			gpio1: bank@1 {
280				reg = <1>;
281				compatible = "mtk,mt7621-gpio-bank";
282				gpio-controller;
283				#gpio-cells = <2>;
284			};
285
286			gpio2: bank@2 {
287				reg = <2>;
288				compatible = "mtk,mt7621-gpio-bank";
289				gpio-controller;
290				#gpio-cells = <2>;
291			};
292		};
293
294		spi0: spi@b00 {
295			compatible = "ralink,mt7621-spi";
296			reg = <0xb00 0x40>;
297
298			resets = <&rstctrl MT7628_SPI_RST>;
299			reset-names = "spi";
300
301			#address-cells = <1>;
302			#size-cells = <0>;
303
304			clocks = <&clkctrl CLK_SPI>;
305		};
306
307		uart0: uartlite@c00 {
308			compatible = "mediatek,hsuart", "ns16550a";
309			reg = <0xc00 0x100>;
310
311			pinctrl-names = "default";
312			pinctrl-0 = <&uart0_pins>;
313
314			clocks = <&clkctrl CLK_UART0>;
315
316			resets = <&rstctrl MT7628_UART0_RST>;
317			reset-names = "uart0";
318
319			interrupt-parent = <&intc>;
320			interrupts = <20>;
321
322			reg-shift = <2>;
323		};
324
325		uart1: uart1@d00 {
326			compatible = "mediatek,hsuart", "ns16550a";
327			reg = <0xd00 0x100>;
328
329			pinctrl-names = "default";
330			pinctrl-0 = <&uart1_pins>;
331
332			clocks = <&clkctrl CLK_UART1>;
333
334			resets = <&rstctrl MT7628_UART1_RST>;
335			reset-names = "uart1";
336
337			interrupt-parent = <&intc>;
338			interrupts = <21>;
339
340			reg-shift = <2>;
341		};
342
343		uart2: uart2@e00 {
344			compatible = "mediatek,hsuart", "ns16550a";
345			reg = <0xe00 0x100>;
346
347			pinctrl-names = "default";
348			pinctrl-0 = <&uart2_pins>;
349
350			clocks = <&clkctrl CLK_UART2>;
351
352			resets = <&rstctrl MT7628_UART2_RST>;
353			reset-names = "uart2";
354
355			interrupt-parent = <&intc>;
356			interrupts = <22>;
357
358			reg-shift = <2>;
359		};
360	};
361
362	eth: eth@10110000 {
363		compatible = "mediatek,mt7628-eth";
364		reg = <0x10100000 0x10000
365		       0x10110000 0x8000>;
366
367		resets = <&rstctrl MT7628_EPHY_RST>;
368		reset-names = "ephy";
369
370		syscon = <&sysc>;
371	};
372
373	usb_phy: usb-phy@10120000 {
374		compatible = "mediatek,mt7628-usbphy";
375		reg = <0x10120000 0x1000>;
376
377		#phy-cells = <0>;
378
379		ralink,sysctl = <&sysc>;
380
381		resets = <&rstctrl MT7628_UPHY_RST>;
382		reset-names = "phy";
383
384		clocks = <&clkctrl CLK_UPHY>;
385		clock-names = "cg";
386	};
387
388	ehci@101c0000 {
389		compatible = "generic-ehci";
390		reg = <0x101c0000 0x1000>;
391
392		phys = <&usb_phy>;
393		phy-names = "usb";
394
395		interrupt-parent = <&intc>;
396		interrupts = <18>;
397	};
398
399	mmc: mmc@10130000 {
400		compatible = "mediatek,mt7620-mmc";
401		reg = <0x10130000 0x4000>;
402		builtin-cd = <1>;
403		r_smpl = <1>;
404
405		clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
406		clock-names = "source", "hclk";
407
408		resets = <&rstctrl MT7628_SDXC_RST>;
409
410		status = "disabled";
411	};
412};
413