1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P1010 Silicon/SoC Device Tree Source (post include)
4 *
5 * Copyright 2020 NXP
6 */
7
8&soc {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	device_type = "soc";
12	compatible = "fsl,p1010-immr", "simple-bus";
13	bus-frequency = <0>;
14
15	mpic: pic@40000 {
16		interrupt-controller;
17		#address-cells = <0>;
18		#interrupt-cells = <4>;
19		reg = <0x40000 0x40000>;
20		compatible = "fsl,mpic";
21		device_type = "open-pic";
22		big-endian;
23		single-cpu-affinity;
24		last-interrupt-source = <255>;
25	};
26
27	espi0: spi@7000 {
28		compatible = "fsl,mpc8536-espi";
29		#address-cells = <1>;
30		#size-cells = <0>;
31		reg = <0x7000 0x1000>;
32		fsl,espi-num-chipselects = <1>;
33		status = "disabled";
34	};
35
36/include/ "pq3-i2c-0.dtsi"
37/include/ "pq3-i2c-1.dtsi"
38
39/include/ "pq3-etsec2-0.dtsi"
40	enet0: ethernet@b0000 {
41		queue-group@b0000 {
42			fsl,rx-bit-map = <0xff>;
43			fsl,tx-bit-map = <0xff>;
44		};
45	};
46
47/include/ "pq3-etsec2-1.dtsi"
48	enet1: ethernet@b1000 {
49		queue-group@b1000 {
50			fsl,rx-bit-map = <0xff>;
51			fsl,tx-bit-map = <0xff>;
52		};
53	};
54
55/include/ "pq3-etsec2-2.dtsi"
56	enet2: ethernet@b2000 {
57		queue-group@b2000 {
58			fsl,rx-bit-map = <0xff>;
59			fsl,tx-bit-map = <0xff>;
60		};
61
62	};
63};
64
65/* controller at 0x9000 */
66&pci1 {
67	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
68	law_trgt_if = <1>;
69	#address-cells = <3>;
70	#size-cells = <2>;
71	device_type = "pci";
72	bus-range = <0x0 0xff>;
73};
74
75/* controller at 0xa000 */
76&pci0 {
77	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
78	law_trgt_if = <2>;
79	#address-cells = <3>;
80	#size-cells = <2>;
81	device_type = "pci";
82	bus-range = <0x0 0xff>;
83};
84