1/*
2 * Copyright (c) 2020, ARM Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * The Arm Ltd. FPGA images start execution at address 0x0, which is
7 * mapped at an (emulated) ROM image. The payload uploader can write to
8 * this memory, but write access by the CPU cores is prohibited.
9 *
10 * Provide a simple trampoline to start BL31 execution at the actual
11 * load address. We put the DTB address in x0, so any code in DRAM could
12 * make use of that information (not yet used in BL31 right now).
13 */
14
15#include <asm_macros.S>
16#include <common/bl_common.ld.h>
17
18.text
19.global _start
20
21_start:
22	mov_imm	x1, BL31_BASE			/* beginning of DRAM */
23	mov_imm	x0, FPGA_PRELOADED_DTB_BASE
24	br	x1
25