1/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
10
11	.globl	plat_reset_handler
12	.globl  plat_my_core_pos
13	.globl  platform_mem_init
14
15func plat_my_core_pos
16	mrs x0, mpidr_el1
17	and x1, x0, #MPIDR_CPU_MASK   //reserve the last 8 bits
18	and x0, x0, #MPIDR_CLUSTER_MASK
19	add x0, x1, x0, LSR #4  //4 cores
20	ret
21endfunc plat_my_core_pos
22
23func platform_mem_init
24	mov x29, x30
25	bl  inv_dcache_range
26
27//SDRAM_CFG
28	ldr w0, =0x1080000
29	ldr w1, =0x0c000c45
30	str w1, [x0, #0x110]
31//CS0_BNDS
32	ldr w1, =0x7f000000
33	str w1, [x0, #0x000]
34//CS0_CONFIG
35	ldr w1, =0x22030480
36	str w1, [x0, #0x080]
37//TIMING_CFG_0
38	ldr w1, =0x18005591
39	str w1, [x0, #0x104]
40//TIMING_CFG_1
41	ldr w1, =0x428cb4bb
42	str w1, [x0, #0x108]
43//TIMING_CFG_2
44	ldr w1, =0x11c14800
45	str w1, [x0, #0x10C]
46//TIMING_CFG_3
47	ldr w1, =0x00100c01
48	str w1, [x0, #0x100]
49//TIMING_CFG_4
50	ldr w1, =0x02000000
51	str w1, [x0, #0x160]
52//TIMING_CFG_5
53	ldr w1, =0x00144003
54	str w1, [x0, #0x164]
55//TIMING_CFG_7
56	ldr w1, =0x00003013
57	str w1, [x0, #0x16C]
58//TIMING_CFG_8
59	ldr w1, =0x00561102
60	str w1, [x0, #0x250]
61//SDRAM_CFG_2
62	ldr w1, =0x00114000
63	str w1, [x0, #0x114]
64//SDRAM_MODE
65	ldr w1, =0x10020103
66	str w1, [x0, #0x118]
67//SDRAM_MODE_2
68	ldr w1, =0x0
69	str w1, [x0, #0x11C]
70//SDRAM_INTERVAL
71	ldr w1, =0x18066018
72	str w1, [x0, #0x124]
73//DDR_WRLVL_CNTL
74	ldr w1, =0x07f675c6
75	str w1, [x0, #0x174]
76//DDR_WRLVL_CNTL_2
77	ldr w1, =0x00080907
78	str w1, [x0, #0x190]
79//DDR_WRLVL_CNTL_3
80	ldr w1, =0x0
81	str w1, [x0, #0x194]
82//DDR_CDR1
83	ldr w1, =0x00000480
84	str w1, [x0, #0xB28]
85//DDR_CDR2
86	ldr w1, =0x81a10000
87	str w1, [x0, #0xB2C]
88//SDRAM_CLK_CNTL
89	ldr w1, =0x00000003
90	str w1, [x0, #0x130]
91//DDR_ZQ_CNTL
92	ldr w1, =0x0507098a
93	str w1, [x0, #0x170]
94//SDRAM_MODE_9
95	ldr w1, =0x00050000
96	str w1, [x0, #0x220]
97//SDRAM_MODE_10
98	ldr w1, =0x00000004
99	str w1, [x0, #0x224]
100//CS0_CONFIG_2
101	ldr w1, =0x0
102	str w1, [x0, #0x0C0]
103//SDRAM_CFG
104	ldr w1, =0x08000cc5
105	str w1, [x0, #0x110]
106
107	mov w3,#0
108	ldr w4,=0xffffff01
109z_loop:
110delay_loop1:
111	sub w4, w4, #1
112	cmp w4, #0
113	b.gt    delay_loop1
114
115	ldr w1, [x0, #0x114]
116	add w3, w3, #1
117	cmp       w1, #0 //'\n'
118	b.eq       1f
119	cmp w3, #20
120	b.gt    1f
121	b z_loop
122
1231:
124	ldr w4,=0xffffff02
125delay_loop2:
126	sub w4, w4, #1
127	cmp w4, #0
128	b.gt        delay_loop2
129
130	ldr w1, =0x00000000
131	str w1, [x0]
132
133	ret x29
134endfunc	platform_mem_init
135
136func apply_platform_errata
137	/*TODO if needed*/
138	ret
139endfunc apply_platform_errata
140
141func plat_reset_handler
142	mov x29, x30
143	bl  apply_platform_errata
144
145	mov x30, x29
146	ret
147endfunc plat_reset_handler
148