1 /*
2  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <common/debug.h>
8 #include <drivers/arm/cci.h>
9 #include <lib/mmio.h>
10 
11 #include "plat_ls.h"
12 
13 static const int cci_map[] = {
14 	PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX
15 };
16 
bl1_platform_setup(void)17 void bl1_platform_setup(void)
18 {
19 	NOTICE(FIRMWARE_WELCOME_STR_LS1043);
20 
21 	ls_bl1_platform_setup();
22 
23 	/*
24 	 * Initialize system level generic timer for Layerscape Socs.
25 	 */
26 	ls_delay_timer_init();
27 
28 	/* TODO: remove these DDR code */
29 	VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
30 	mmio_write_32(0x1080000 + 0x000, 0x7f000000);
31 	VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
32 }
33 
34 /*******************************************************************************
35  * Perform any BL1 specific platform actions.
36  ******************************************************************************/
bl1_early_platform_setup(void)37 void bl1_early_platform_setup(void)
38 {
39 	ls_bl1_early_platform_setup();
40 
41 	/*
42 	 * Initialize Interconnect for this cluster during cold boot.
43 	 * No need for locks as no other CPU is active.
44 	 */
45 	cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
46 
47 	/*
48 	 * Enable coherency in Interconnect for the primary CPU's cluster.
49 	 */
50 	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
51 
52 }
53 
bl1_plat_get_next_image_id(void)54 unsigned int bl1_plat_get_next_image_id(void)
55 {
56 	return BL2_IMAGE_ID;
57 }
58