1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef PLAT_DEFAULT_DEF_H 9 #define PLAT_DEFAULT_DEF_H 10 11 /* 12 * Platform binary types for linking 13 */ 14 #ifdef __aarch64__ 15 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16 #define PLATFORM_LINKER_ARCH aarch64 17 #else 18 #define PLATFORM_LINKER_FORMAT "elf32-littlearm" 19 #define PLATFORM_LINKER_ARCH arm 20 #endif /* __aarch64__ */ 21 22 #define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 23 24 /* NXP Platforms have DRAM divided into banks. 25 * DRAM0 Bank: Maximum size of this bank is fixed to 2GB 26 * DRAM1 Bank: Greater than 2GB belongs to bank1 and size of bank1 varies from 27 * one platform to other platform. 28 * DRAMn Bank: 29 * 30 * Except a few, all the platforms have 2GB size as DRAM0 BANK. 31 * Hence common for all the platforms. 32 * For platforms where DRAM0 Size is < 2GB, it is defined in platform_def.h 33 */ 34 #ifndef PLAT_DEF_DRAM0_SIZE 35 #define PLAT_DEF_DRAM0_SIZE 0x80000000 /* 2G */ 36 #endif 37 38 /* This is common for all platforms where: */ 39 #ifndef NXP_NS_DRAM_ADDR 40 #define NXP_NS_DRAM_ADDR NXP_DRAM0_ADDR 41 #endif 42 43 /* 64M is reserved for Secure memory 44 */ 45 #ifndef NXP_SECURE_DRAM_SIZE 46 #define NXP_SECURE_DRAM_SIZE (64 * 1024 * 1024) 47 #endif 48 49 /* 2M Secure EL1 Payload Shared Memory */ 50 #ifndef NXP_SP_SHRD_DRAM_SIZE 51 #define NXP_SP_SHRD_DRAM_SIZE (2 * 1024 * 1024) 52 #endif 53 54 #ifndef NXP_NS_DRAM_SIZE 55 /* Non secure memory */ 56 #define NXP_NS_DRAM_SIZE (PLAT_DEF_DRAM0_SIZE - \ 57 (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) 58 #endif 59 60 #ifndef NXP_SECURE_DRAM_ADDR 61 #ifdef TEST_BL31 62 #define NXP_SECURE_DRAM_ADDR 0 63 #else 64 #define NXP_SECURE_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \ 65 (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) 66 #endif 67 #endif 68 69 #ifndef NXP_SP_SHRD_DRAM_ADDR 70 #define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE \ 71 - NXP_SP_SHRD_DRAM_SIZE) 72 #endif 73 74 #ifndef BL31_BASE 75 /* 2 MB reserved in secure memory for DDR */ 76 #define BL31_BASE NXP_SECURE_DRAM_ADDR 77 #endif 78 79 #ifndef BL31_SIZE 80 #define BL31_SIZE (0x200000) 81 #endif 82 83 #ifndef BL31_LIMIT 84 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 85 #endif 86 87 /* Put BL32 in secure memory */ 88 #ifndef BL32_BASE 89 #define BL32_BASE (NXP_SECURE_DRAM_ADDR + BL31_SIZE) 90 #endif 91 92 #ifndef BL32_LIMIT 93 #define BL32_LIMIT (NXP_SECURE_DRAM_ADDR + \ 94 NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE) 95 #endif 96 97 /* BL33 memory region */ 98 /* Hardcoded based on current address in u-boot */ 99 #ifndef BL33_BASE 100 #define BL33_BASE 0x82000000 101 #endif 102 103 #ifndef BL33_LIMIT 104 #define BL33_LIMIT (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE) 105 #endif 106 107 /* 108 * FIP image defines - Offset at which FIP Image would be present 109 * Image would include Bl31 , Bl33 and Bl32 (optional) 110 */ 111 #ifdef POLICY_FUSE_PROVISION 112 #ifndef FUSE_BUF 113 #define FUSE_BUF ULL(0x81000000) 114 #endif 115 116 #ifndef FUSE_SZ 117 #define FUSE_SZ 0x80000 118 #endif 119 #endif 120 121 #ifndef MAX_FIP_DEVICES 122 #define MAX_FIP_DEVICES 2 123 #endif 124 125 #ifndef PLAT_FIP_OFFSET 126 #define PLAT_FIP_OFFSET 0x100000 127 #endif 128 129 #ifndef PLAT_FIP_MAX_SIZE 130 #define PLAT_FIP_MAX_SIZE 0x400000 131 #endif 132 133 /* Check if this size can be determined from array size */ 134 #if defined(IMAGE_BL2) 135 #ifndef MAX_MMAP_REGIONS 136 #define MAX_MMAP_REGIONS 8 137 #endif 138 #ifndef MAX_XLAT_TABLES 139 #define MAX_XLAT_TABLES 6 140 #endif 141 #elif defined(IMAGE_BL31) 142 #ifndef MAX_MMAP_REGIONS 143 #define MAX_MMAP_REGIONS 9 144 #endif 145 #ifndef MAX_XLAT_TABLES 146 #define MAX_XLAT_TABLES 9 147 #endif 148 #elif defined(IMAGE_BL32) 149 #ifndef MAX_MMAP_REGIONS 150 #define MAX_MMAP_REGIONS 8 151 #endif 152 #ifndef MAX_XLAT_TABLES 153 #define MAX_XLAT_TABLES 9 154 #endif 155 #endif 156 157 /* 158 * ID of the secure physical generic timer interrupt used by the BL32. 159 */ 160 #ifndef BL32_IRQ_SEC_PHY_TIMER 161 #define BL32_IRQ_SEC_PHY_TIMER 29 162 #endif 163 164 #endif /* PLAT_DEFAULT_DEF_H */ 165