1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a copy 3 * of this software and associated documentation files (the "Software"), to 4 * deal in the Software without restriction, including without limitation the 5 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 6 * sell copies of the Software, and to permit persons to whom the Software is 7 * furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 15 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 16 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 17 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 18 * DEALINGS IN THE SOFTWARE. 19 * 20 * Copyright (c) 2007, Keir Fraser 21 */ 22 23 #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ 24 #define __XEN_PUBLIC_HVM_PARAMS_H__ 25 26 #include "hvm_op.h" 27 28 /* These parameters are deprecated and their meaning is undefined. */ 29 #if defined(__XEN__) || defined(__XEN_TOOLS__) 30 31 #define HVM_PARAM_PAE_ENABLED 4 32 #define HVM_PARAM_DM_DOMAIN 13 33 #define HVM_PARAM_MEMORY_EVENT_CR0 20 34 #define HVM_PARAM_MEMORY_EVENT_CR3 21 35 #define HVM_PARAM_MEMORY_EVENT_CR4 22 36 #define HVM_PARAM_MEMORY_EVENT_INT3 23 37 #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP 25 38 #define HVM_PARAM_BUFIOREQ_EVTCHN 26 39 #define HVM_PARAM_MEMORY_EVENT_MSR 30 40 41 #endif /* defined(__XEN__) || defined(__XEN_TOOLS__) */ 42 43 /* 44 * Parameter space for HVMOP_{set,get}_param. 45 */ 46 47 #define HVM_PARAM_CALLBACK_IRQ 0 48 #define HVM_PARAM_CALLBACK_IRQ_TYPE_MASK xen_mk_ullong(0xFF00000000000000) 49 /* 50 * How should CPU0 event-channel notifications be delivered? 51 * 52 * If val == 0 then CPU0 event-channel notifications are not delivered. 53 * If val != 0, val[63:56] encodes the type, as follows: 54 */ 55 56 #define HVM_PARAM_CALLBACK_TYPE_GSI 0 57 /* 58 * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, 59 * and disables all notifications. 60 */ 61 62 #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 63 /* 64 * val[55:0] is a delivery PCI INTx line: 65 * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] 66 */ 67 68 #if defined(__i386__) || defined(__x86_64__) 69 #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 70 /* 71 * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know 72 * if this delivery method is available. 73 */ 74 #elif defined(__arm__) || defined(__aarch64__) 75 #define HVM_PARAM_CALLBACK_TYPE_PPI 2 76 /* 77 * val[55:16] needs to be zero. 78 * val[15:8] is interrupt flag of the PPI used by event-channel: 79 * bit 8: the PPI is edge(1) or level(0) triggered 80 * bit 9: the PPI is active low(1) or high(0) 81 * val[7:0] is a PPI number used by event-channel. 82 * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to 83 * the notification is handled by the interrupt controller. 84 */ 85 #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK 0xFF00 86 #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL 2 87 #endif 88 89 /* 90 * These are not used by Xen. They are here for convenience of HVM-guest 91 * xenbus implementations. 92 */ 93 #define HVM_PARAM_STORE_PFN 1 94 #define HVM_PARAM_STORE_EVTCHN 2 95 96 #define HVM_PARAM_IOREQ_PFN 5 97 98 #define HVM_PARAM_BUFIOREQ_PFN 6 99 100 #if defined(__i386__) || defined(__x86_64__) 101 102 /* 103 * Viridian enlightenments 104 * 105 * (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hypervisor%20Top%20Level%20Functional%20Specification%20v4.0.docx) 106 * 107 * To expose viridian enlightenments to the guest set this parameter 108 * to the desired feature mask. The base feature set must be present 109 * in any valid feature mask. 110 */ 111 #define HVM_PARAM_VIRIDIAN 9 112 113 /* Base+Freq viridian feature sets: 114 * 115 * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) 116 * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 117 * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX) 118 * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and 119 * HV_X64_MSR_APIC_FREQUENCY) 120 */ 121 #define _HVMPV_base_freq 0 122 #define HVMPV_base_freq (1 << _HVMPV_base_freq) 123 124 /* Feature set modifications */ 125 126 /* Disable timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and 127 * HV_X64_MSR_APIC_FREQUENCY). 128 * This modification restores the viridian feature set to the 129 * original 'base' set exposed in releases prior to Xen 4.4. 130 */ 131 #define _HVMPV_no_freq 1 132 #define HVMPV_no_freq (1 << _HVMPV_no_freq) 133 134 /* Enable Partition Time Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */ 135 #define _HVMPV_time_ref_count 2 136 #define HVMPV_time_ref_count (1 << _HVMPV_time_ref_count) 137 138 /* Enable Reference TSC Page (HV_X64_MSR_REFERENCE_TSC) */ 139 #define _HVMPV_reference_tsc 3 140 #define HVMPV_reference_tsc (1 << _HVMPV_reference_tsc) 141 142 /* Use Hypercall for remote TLB flush */ 143 #define _HVMPV_hcall_remote_tlb_flush 4 144 #define HVMPV_hcall_remote_tlb_flush (1 << _HVMPV_hcall_remote_tlb_flush) 145 146 /* Use APIC assist */ 147 #define _HVMPV_apic_assist 5 148 #define HVMPV_apic_assist (1 << _HVMPV_apic_assist) 149 150 /* Enable crash MSRs */ 151 #define _HVMPV_crash_ctl 6 152 #define HVMPV_crash_ctl (1 << _HVMPV_crash_ctl) 153 154 /* Enable SYNIC MSRs */ 155 #define _HVMPV_synic 7 156 #define HVMPV_synic (1 << _HVMPV_synic) 157 158 /* Enable STIMER MSRs */ 159 #define _HVMPV_stimer 8 160 #define HVMPV_stimer (1 << _HVMPV_stimer) 161 162 /* Use Synthetic Cluster IPI Hypercall */ 163 #define _HVMPV_hcall_ipi 9 164 #define HVMPV_hcall_ipi (1 << _HVMPV_hcall_ipi) 165 166 #define HVMPV_feature_mask \ 167 (HVMPV_base_freq | \ 168 HVMPV_no_freq | \ 169 HVMPV_time_ref_count | \ 170 HVMPV_reference_tsc | \ 171 HVMPV_hcall_remote_tlb_flush | \ 172 HVMPV_apic_assist | \ 173 HVMPV_crash_ctl | \ 174 HVMPV_synic | \ 175 HVMPV_stimer | \ 176 HVMPV_hcall_ipi) 177 178 #endif 179 180 /* 181 * Set mode for virtual timers (currently x86 only): 182 * delay_for_missed_ticks (default): 183 * Do not advance a vcpu's time beyond the correct delivery time for 184 * interrupts that have been missed due to preemption. Deliver missed 185 * interrupts when the vcpu is rescheduled and advance the vcpu's virtual 186 * time stepwise for each one. 187 * no_delay_for_missed_ticks: 188 * As above, missed interrupts are delivered, but guest time always tracks 189 * wallclock (i.e., real) time while doing so. 190 * no_missed_ticks_pending: 191 * No missed interrupts are held pending. Instead, to ensure ticks are 192 * delivered at some non-zero rate, if we detect missed ticks then the 193 * internal tick alarm is not disabled if the VCPU is preempted during the 194 * next tick period. 195 * one_missed_tick_pending: 196 * Missed interrupts are collapsed together and delivered as one 'late tick'. 197 * Guest time always tracks wallclock (i.e., real) time. 198 */ 199 #define HVM_PARAM_TIMER_MODE 10 200 #define HVMPTM_delay_for_missed_ticks 0 201 #define HVMPTM_no_delay_for_missed_ticks 1 202 #define HVMPTM_no_missed_ticks_pending 2 203 #define HVMPTM_one_missed_tick_pending 3 204 205 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ 206 #define HVM_PARAM_HPET_ENABLED 11 207 208 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ 209 #define HVM_PARAM_IDENT_PT 12 210 211 /* ACPI S state: currently support S0 and S3 on x86. */ 212 #define HVM_PARAM_ACPI_S_STATE 14 213 214 /* TSS used on Intel when CR0.PE=0. */ 215 #define HVM_PARAM_VM86_TSS 15 216 217 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ 218 #define HVM_PARAM_VPT_ALIGN 16 219 220 /* Console debug shared memory ring and event channel */ 221 #define HVM_PARAM_CONSOLE_PFN 17 222 #define HVM_PARAM_CONSOLE_EVTCHN 18 223 224 /* 225 * Select location of ACPI PM1a and TMR control blocks. Currently two locations 226 * are supported, specified by version 0 or 1 in this parameter: 227 * - 0: default, use the old addresses 228 * PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48 229 * - 1: use the new default qemu addresses 230 * PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008 231 * You can find these address definitions in <hvm/ioreq.h> 232 */ 233 #define HVM_PARAM_ACPI_IOPORTS_LOCATION 19 234 235 /* Boolean: Enable nestedhvm (hvm only) */ 236 #define HVM_PARAM_NESTEDHVM 24 237 238 /* Params for the mem event rings */ 239 #define HVM_PARAM_PAGING_RING_PFN 27 240 #define HVM_PARAM_MONITOR_RING_PFN 28 241 #define HVM_PARAM_SHARING_RING_PFN 29 242 243 /* SHUTDOWN_* action in case of a triple fault */ 244 #define HVM_PARAM_TRIPLE_FAULT_REASON 31 245 246 #define HVM_PARAM_IOREQ_SERVER_PFN 32 247 #define HVM_PARAM_NR_IOREQ_SERVER_PAGES 33 248 249 /* Location of the VM Generation ID in guest physical address space. */ 250 #define HVM_PARAM_VM_GENERATION_ID_ADDR 34 251 252 /* 253 * Set mode for altp2m: 254 * disabled: don't activate altp2m (default) 255 * mixed: allow access to all altp2m ops for both in-guest and external tools 256 * external: allow access to external privileged tools only 257 * limited: guest only has limited access (ie. control VMFUNC and #VE) 258 * 259 * Note that 'mixed' mode has not been evaluated for safety from a 260 * security perspective. Before using this mode in a 261 * security-critical environment, each subop should be evaluated for 262 * safety, with unsafe subops blacklisted in XSM. 263 */ 264 #define HVM_PARAM_ALTP2M 35 265 #define XEN_ALTP2M_disabled 0 266 #define XEN_ALTP2M_mixed 1 267 #define XEN_ALTP2M_external 2 268 #define XEN_ALTP2M_limited 3 269 270 /* 271 * Size of the x87 FPU FIP/FDP registers that the hypervisor needs to 272 * save/restore. This is a workaround for a hardware limitation that 273 * does not allow the full FIP/FDP and FCS/FDS to be restored. 274 * 275 * Valid values are: 276 * 277 * 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU 278 * has FPCSDS feature). 279 * 280 * 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of 281 * FIP/FDP. 282 * 283 * 0: allow hypervisor to choose based on the value of FIP/FDP 284 * (default if CPU does not have FPCSDS). 285 * 286 * If FPCSDS (bit 13 in CPUID leaf 0x7, subleaf 0x0) is set, the CPU 287 * never saves FCS/FDS and this parameter should be left at the 288 * default of 8. 289 */ 290 #define HVM_PARAM_X87_FIP_WIDTH 36 291 292 /* 293 * TSS (and its size) used on Intel when CR0.PE=0. The address occupies 294 * the low 32 bits, while the size is in the high 32 ones. 295 */ 296 #define HVM_PARAM_VM86_TSS_SIZED 37 297 298 /* Enable MCA capabilities. */ 299 #define HVM_PARAM_MCA_CAP 38 300 #define XEN_HVM_MCA_CAP_LMCE (xen_mk_ullong(1) << 0) 301 #define XEN_HVM_MCA_CAP_MASK XEN_HVM_MCA_CAP_LMCE 302 303 #define HVM_NR_PARAMS 39 304 305 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ 306