1/*
2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018,2020, The Linux Foundation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <arch.h>
9#include <asm_macros.S>
10#include <drivers/arm/gicv2.h>
11#include <drivers/arm/gicv3.h>
12#include <drivers/console.h>
13
14#include <platform_def.h>
15
16	.globl	plat_my_core_pos
17	.globl	plat_qti_core_pos_by_mpidr
18	.globl	plat_reset_handler
19	.globl	plat_panic_handler
20
21	/* -----------------------------------------------------
22	 *  unsigned int plat_qti_core_pos_by_mpidr(uint64_t mpidr)
23	 *  Helper function to calculate the core position.
24	 *  With this function:
25	 *  CorePos = (ClusterId * 4) + CoreId
26	 *  - In ARM v8   (MPIDR_EL1[24]=0)
27	 *    ClusterId = MPIDR_EL1[15:8]
28	 *    CoreId    = MPIDR_EL1[7:0]
29	 *  - In ARM v8.1 (MPIDR_EL1[24]=1)
30	 *    ClusterId = MPIDR_EL1[23:15]
31	 *    CoreId    = MPIDR_EL1[15:8]
32	 *  Clobbers: x0 & x1.
33	 * -----------------------------------------------------
34	 */
35func plat_qti_core_pos_by_mpidr
36	mrs	x1, mpidr_el1
37	tst	x1, #MPIDR_MT_MASK
38	beq	plat_qti_core_pos_by_mpidr_no_mt
39	/* Right shift mpidr by one affinity level when MT=1. */
40	lsr	x0, x0, #MPIDR_AFFINITY_BITS
41plat_qti_core_pos_by_mpidr_no_mt:
42	and	x1, x0, #MPIDR_CPU_MASK
43	and	x0, x0, #MPIDR_CLUSTER_MASK
44	add	x0, x1, x0, LSR #6
45	ret
46endfunc plat_qti_core_pos_by_mpidr
47
48	/* --------------------------------------------------------------------
49	 * void plat_panic_handler(void)
50	 * calls SDI and reset system
51	 * --------------------------------------------------------------------
52	 */
53func plat_panic_handler
54	msr	spsel, #0
55	bl	plat_set_my_stack
56	b	qtiseclib_panic
57endfunc plat_panic_handler
58
59	/* -----------------------------------------------------
60	 *  unsigned int plat_my_core_pos(void)
61	 *  This function uses the plat_qti_calc_core_pos()
62	 *  definition to get the index of the calling CPU
63	 *  Clobbers: x0 & x1.
64	 * -----------------------------------------------------
65	 */
66func plat_my_core_pos
67	mrs	x0, mpidr_el1
68	b	plat_qti_core_pos_by_mpidr
69endfunc plat_my_core_pos
70
71func plat_reset_handler
72	/* save the lr */
73	mov	x18, x30
74
75	/* Serialize CPUSS boot setup. Multi core enter simultaneously. */
76	ldr	x0, =g_qti_cpuss_boot_lock
77	bl	spin_lock
78
79	/* pass cold boot status. */
80	ldr	w0, g_qti_bl31_cold_booted
81	/* Execuete CPUSS boot set up on every core. */
82	bl	qtiseclib_cpuss_reset_asm
83
84	ldr	x0, =g_qti_cpuss_boot_lock
85	bl	spin_unlock
86
87	ret	x18
88endfunc plat_reset_handler
89