1 /*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <plat/arm/common/plat_arm.h>
12 #include <plat/common/platform.h>
13 #include <drivers/arm/sbsa.h>
14
15 #if SPM_MM
16 #include <services/spm_mm_partition.h>
17 #endif
18
19 /*
20 * Table of regions for different BL stages to map using the MMU.
21 */
22 #if IMAGE_BL1
23 const mmap_region_t plat_arm_mmap[] = {
24 ARM_MAP_SHARED_RAM,
25 SGI_MAP_FLASH0_RO,
26 CSS_SGI_MAP_DEVICE,
27 SOC_PLATFORM_PERIPH_MAP_DEVICE,
28 SOC_SYSTEM_PERIPH_MAP_DEVICE,
29 {0}
30 };
31 #endif
32
33 #if IMAGE_BL2
34 const mmap_region_t plat_arm_mmap[] = {
35 ARM_MAP_SHARED_RAM,
36 SGI_MAP_FLASH0_RO,
37 #ifdef PLAT_ARM_MEM_PROT_ADDR
38 ARM_V2M_MAP_MEM_PROTECT,
39 #endif
40 CSS_SGI_MAP_DEVICE,
41 SOC_MEMCNTRL_MAP_DEVICE,
42 SOC_PLATFORM_PERIPH_MAP_DEVICE,
43 SOC_SYSTEM_PERIPH_MAP_DEVICE,
44 ARM_MAP_NS_DRAM1,
45 #if ARM_BL31_IN_DRAM
46 ARM_MAP_BL31_SEC_DRAM,
47 #endif
48 #if SPM_MM
49 ARM_SP_IMAGE_MMAP,
50 #endif
51 #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
52 ARM_MAP_BL1_RW,
53 #endif
54 {0}
55 };
56 #endif
57
58 #if IMAGE_BL31
59 const mmap_region_t plat_arm_mmap[] = {
60 ARM_MAP_SHARED_RAM,
61 #ifdef PLAT_ARM_MEM_PROT_ADDR
62 ARM_V2M_MAP_MEM_PROTECT,
63 #endif
64 CSS_SGI_MAP_DEVICE,
65 SOC_PLATFORM_PERIPH_MAP_DEVICE,
66 SOC_SYSTEM_PERIPH_MAP_DEVICE,
67 #if SPM_MM
68 ARM_SPM_BUF_EL3_MMAP,
69 #endif
70 {0}
71 };
72
73 #if SPM_MM && defined(IMAGE_BL31)
74 const mmap_region_t plat_arm_secure_partition_mmap[] = {
75 PLAT_ARM_SECURE_MAP_SYSTEMREG,
76 PLAT_ARM_SECURE_MAP_NOR2,
77 SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
78 ARM_SP_IMAGE_MMAP,
79 ARM_SP_IMAGE_NS_BUF_MMAP,
80 ARM_SP_IMAGE_RW_MMAP,
81 ARM_SPM_BUF_EL0_MMAP,
82 {0}
83 };
84 #endif /* SPM_MM && defined(IMAGE_BL31) */
85 #endif
86
87 ARM_CASSERT_MMAP
88
89 #if SPM_MM && defined(IMAGE_BL31)
90 /*
91 * Boot information passed to a secure partition during initialisation. Linear
92 * indices in MP information will be filled at runtime.
93 */
94 static spm_mm_mp_info_t sp_mp_info[] = {
95 [0] = {0x81000000, 0},
96 [1] = {0x81010000, 0},
97 [2] = {0x81020000, 0},
98 [3] = {0x81030000, 0},
99 [4] = {0x81040000, 0},
100 [5] = {0x81050000, 0},
101 [6] = {0x81060000, 0},
102 [7] = {0x81070000, 0},
103 [8] = {0x81080000, 0},
104 [9] = {0x81090000, 0},
105 [10] = {0x810a0000, 0},
106 [11] = {0x810b0000, 0},
107 [12] = {0x810c0000, 0},
108 [13] = {0x810d0000, 0},
109 [14] = {0x810e0000, 0},
110 [15] = {0x810f0000, 0},
111 };
112
113 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
114 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
115 .h.version = VERSION_1,
116 .h.size = sizeof(spm_mm_boot_info_t),
117 .h.attr = 0,
118 .sp_mem_base = ARM_SP_IMAGE_BASE,
119 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
120 .sp_image_base = ARM_SP_IMAGE_BASE,
121 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
122 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
123 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
124 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
125 .sp_image_size = ARM_SP_IMAGE_SIZE,
126 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
127 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
128 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
129 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
130 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
131 .num_cpus = PLATFORM_CORE_COUNT,
132 .mp_info = &sp_mp_info[0],
133 };
134
plat_get_secure_partition_mmap(void * cookie)135 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
136 {
137 return plat_arm_secure_partition_mmap;
138 }
139
plat_get_secure_partition_boot_info(void * cookie)140 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
141 void *cookie)
142 {
143 return &plat_arm_secure_partition_boot_info;
144 }
145 #endif /* SPM_MM && defined(IMAGE_BL31) */
146
147 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)148 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
149 {
150 assert(heap_addr != NULL);
151 assert(heap_size != NULL);
152
153 return arm_get_mbedtls_heap(heap_addr, heap_size);
154 }
155 #endif
156
plat_arm_secure_wdt_start(void)157 void plat_arm_secure_wdt_start(void)
158 {
159 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
160 }
161
plat_arm_secure_wdt_stop(void)162 void plat_arm_secure_wdt_stop(void)
163 {
164 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
165 }
166