1 /*
2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <bl31/interrupt_mgmt.h>
11 #include <lib/el3_runtime/context_mgmt.h>
12 #include <lib/extensions/ras.h>
13 #include <plat/arm/common/arm_spm_def.h>
14 #include <plat/common/platform.h>
15 #include <services/sdei.h>
16 #include <services/spm_mm_svc.h>
17
18 #include <sgi_ras.h>
19
20 static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
21 int probe_data,
22 const struct err_handler_data *const data);
23 typedef struct mm_communicate_header {
24 struct efi_guid header_guid;
25 size_t message_len;
26 uint8_t data[8];
27 } mm_communicate_header_t;
28
29 /*
30 * GUID to indicate that the MM communication message is intended for DMC-620
31 * MM driver.
32 */
33 const struct efi_guid dmc620_ecc_event_guid = {
34 0x5ef0afd5, 0xe01a, 0x4c30,
35 {0x86, 0x19, 0x45, 0x46, 0x26, 0x91, 0x80, 0x98}
36 };
37
38 struct sgi_ras_ev_map sgi575_ras_map[] = {
39
40 /* DMC 0 error ECC error interrupt*/
41 {SGI_SDEI_DS_EVENT_0, 35},
42
43 /* DMC 1 error ECC error interrupt*/
44 {SGI_SDEI_DS_EVENT_1, 39},
45 };
46
47 #define SGI575_RAS_MAP_SIZE ARRAY_SIZE(sgi575_ras_map)
48
49 struct err_record_info sgi_err_records[] = {
50 {
51 /* DMC 0 error record info */
52 .handler = &sgi_ras_intr_handler,
53 .aux_data = (void *)0,
54 }, {
55 /* DMC 1 error record info */
56 .handler = &sgi_ras_intr_handler,
57 .aux_data = (void *)1,
58 },
59 };
60
61 struct ras_interrupt sgi_ras_interrupts[] = {
62 {
63 .intr_number = 35,
64 .err_record = &sgi_err_records[0],
65 }, {
66 .intr_number = 39,
67 .err_record = &sgi_err_records[1],
68 }
69 };
70
71 REGISTER_ERR_RECORD_INFO(sgi_err_records);
72 REGISTER_RAS_INTERRUPTS(sgi_ras_interrupts);
73
plat_sgi_get_ras_ev_map(void)74 static struct sgi_ras_ev_map *plat_sgi_get_ras_ev_map(void)
75 {
76 return sgi575_ras_map;
77 }
78
plat_sgi_get_ras_ev_map_size(void)79 static int plat_sgi_get_ras_ev_map_size(void)
80 {
81 return SGI575_RAS_MAP_SIZE;
82 }
83
84 /*
85 * Find event mapping for a given interrupt number: On success, returns pointer
86 * to the event mapping. On error, returns NULL.
87 */
find_ras_event_map_by_intr(uint32_t intr_num)88 static struct sgi_ras_ev_map *find_ras_event_map_by_intr(uint32_t intr_num)
89 {
90 struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
91 int i;
92 int size = plat_sgi_get_ras_ev_map_size();
93
94 for (i = 0; i < size; i++) {
95 if (map->intr == intr_num)
96 return map;
97
98 map++;
99 }
100
101 return NULL;
102 }
103
sgi_ras_intr_configure(int intr)104 static void sgi_ras_intr_configure(int intr)
105 {
106 plat_ic_set_interrupt_type(intr, INTR_TYPE_EL3);
107 plat_ic_set_interrupt_priority(intr, PLAT_RAS_PRI);
108 plat_ic_clear_interrupt_pending(intr);
109 plat_ic_set_spi_routing(intr, INTR_ROUTING_MODE_ANY,
110 (u_register_t)read_mpidr_el1());
111 plat_ic_enable_interrupt(intr);
112 }
113
sgi_ras_intr_handler(const struct err_record_info * err_rec,int probe_data,const struct err_handler_data * const data)114 static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
115 int probe_data,
116 const struct err_handler_data *const data)
117 {
118 struct sgi_ras_ev_map *ras_map;
119 mm_communicate_header_t *header;
120 uint32_t intr;
121 int ret;
122
123 cm_el1_sysregs_context_save(NON_SECURE);
124 intr = data->interrupt;
125
126 /*
127 * Find if this is a RAS interrupt. There must be an event against
128 * this interrupt
129 */
130 ras_map = find_ras_event_map_by_intr(intr);
131 assert(ras_map != NULL);
132
133 /*
134 * Populate the MM_COMMUNICATE payload to share the
135 * event info with StandaloneMM code. This allows us to use
136 * MM_COMMUNICATE as a common entry mechanism into S-EL0. The
137 * header data will be parsed in StandaloneMM to process the
138 * corresponding event.
139 *
140 * TBD - Currently, the buffer allocated by SPM for communication
141 * between EL3 and S-EL0 is being used(PLAT_SPM_BUF_BASE). But this
142 * should happen via a dynamic mem allocation, which should be
143 * managed by SPM -- the individual platforms then call the mem
144 * alloc api to get memory for the payload.
145 */
146 header = (void *) PLAT_SPM_BUF_BASE;
147 memset(header, 0, sizeof(*header));
148 memcpy(&header->data, &err_rec->aux_data, sizeof(err_rec->aux_data));
149 header->message_len = sizeof(err_rec->aux_data);
150 memcpy(&header->header_guid, (void *) &dmc620_ecc_event_guid,
151 sizeof(const struct efi_guid));
152
153 spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
154 plat_my_core_pos());
155
156 /*
157 * Do an EOI of the RAS interrupt. This allows the
158 * sdei event to be dispatched at the SDEI event's
159 * priority.
160 */
161 plat_ic_end_of_interrupt(intr);
162
163 /* Dispatch the event to the SDEI client */
164 ret = sdei_dispatch_event(ras_map->sdei_ev_num);
165 if (ret != 0) {
166 /*
167 * sdei_dispatch_event() may return failing result in some cases,
168 * for example kernel may not have registered a handler or RAS event
169 * may happen early during boot. We restore the NS context when
170 * sdei_dispatch_event() returns failing result.
171 */
172 ERROR("SDEI dispatch failed: %d", ret);
173 cm_el1_sysregs_context_restore(NON_SECURE);
174 cm_set_next_eret_context(NON_SECURE);
175 }
176
177 return ret;
178 }
179
sgi_ras_intr_handler_setup(void)180 int sgi_ras_intr_handler_setup(void)
181 {
182 int i;
183 struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
184 int size = plat_sgi_get_ras_ev_map_size();
185
186 for (i = 0; i < size; i++) {
187 sgi_ras_intr_configure(map->intr);
188 map++;
189 }
190
191 INFO("SGI: RAS Interrupt Handler successfully registered\n");
192
193 return 0;
194 }
195