1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2006
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003 Motorola Inc.
10 * Xianghua Xiao (X.Xiao@motorola.com)
11 */
12
13 #ifndef CONFIG_MPC83XX_SDRAM
14
15 #include <common.h>
16 #include <cpu_func.h>
17 #include <log.h>
18 #include <time.h>
19 #include <vsprintf.h>
20 #include <asm/processor.h>
21 #include <asm/io.h>
22 #include <i2c.h>
23 #include <spd.h>
24 #include <asm/mmu.h>
25 #include <spd_sdram.h>
26 #include <asm/bitops.h>
27 #include <asm/global_data.h>
28 #include <linux/delay.h>
29
30 DECLARE_GLOBAL_DATA_PTR;
31
board_add_ram_info(int use_default)32 void board_add_ram_info(int use_default)
33 {
34 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
35 volatile ddr83xx_t *ddr = &immap->ddr;
36 char buf[32];
37
38 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
39 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
40
41 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
42 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
43 puts(", 16-bit");
44 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
45 puts(", 32-bit");
46 else
47 puts(", unknown width");
48 #else
49 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
50 puts(", 32-bit");
51 else
52 puts(", 64-bit");
53 #endif
54
55 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
56 puts(", ECC on");
57 else
58 puts(", ECC off");
59
60 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
61
62 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
63 puts("\nSDRAM: ");
64 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
65 #endif
66 }
67
68 #ifdef CONFIG_SPD_EEPROM
69 #ifndef CONFIG_SYS_READ_SPD
70 #define CONFIG_SYS_READ_SPD i2c_read
71 #endif
72 #ifndef SPD_EEPROM_OFFSET
73 #define SPD_EEPROM_OFFSET 0
74 #endif
75 #ifndef SPD_EEPROM_ADDR_LEN
76 #define SPD_EEPROM_ADDR_LEN 1
77 #endif
78
79 /*
80 * Convert picoseconds into clock cycles (rounding up if needed).
81 */
82 int
picos_to_clk(int picos)83 picos_to_clk(int picos)
84 {
85 unsigned int mem_bus_clk;
86 int clks;
87
88 mem_bus_clk = gd->mem_clk >> 1;
89 clks = picos / (1000000000 / (mem_bus_clk / 1000));
90 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
91 clks++;
92
93 return clks;
94 }
95
banksize(unsigned char row_dens)96 unsigned int banksize(unsigned char row_dens)
97 {
98 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
99 }
100
read_spd(uint addr)101 int read_spd(uint addr)
102 {
103 return ((int) addr);
104 }
105
106 #undef SPD_DEBUG
107 #ifdef SPD_DEBUG
spd_debug(spd_eeprom_t * spd)108 static void spd_debug(spd_eeprom_t *spd)
109 {
110 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
111 printf ("SPD size: %d\n", spd->info_size);
112 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
113 printf ("Memory type: %d\n", spd->mem_type);
114 printf ("Row addr: %d\n", spd->nrow_addr);
115 printf ("Column addr: %d\n", spd->ncol_addr);
116 printf ("# of rows: %d\n", spd->nrows);
117 printf ("Row density: %d\n", spd->row_dens);
118 printf ("# of banks: %d\n", spd->nbanks);
119 printf ("Data width: %d\n",
120 256 * spd->dataw_msb + spd->dataw_lsb);
121 printf ("Chip width: %d\n", spd->primw);
122 printf ("Refresh rate: %02X\n", spd->refresh);
123 printf ("CAS latencies: %02X\n", spd->cas_lat);
124 printf ("Write latencies: %02X\n", spd->write_lat);
125 printf ("tRP: %d\n", spd->trp);
126 printf ("tRCD: %d\n", spd->trcd);
127 printf ("\n");
128 }
129 #endif /* SPD_DEBUG */
130
spd_sdram()131 long int spd_sdram()
132 {
133 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
134 volatile ddr83xx_t *ddr = &immap->ddr;
135 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
136 spd_eeprom_t spd;
137 unsigned int n_ranks;
138 unsigned int odt_rd_cfg, odt_wr_cfg;
139 unsigned char twr_clk, twtr_clk;
140 unsigned int sdram_type;
141 unsigned int memsize;
142 unsigned int law_size;
143 unsigned char caslat, caslat_ctrl;
144 unsigned int trfc, trfc_clk, trfc_low;
145 unsigned int trcd_clk, trtp_clk;
146 unsigned char cke_min_clk;
147 unsigned char add_lat, wr_lat;
148 unsigned char wr_data_delay;
149 unsigned char four_act;
150 unsigned char cpo;
151 unsigned char burstlen;
152 unsigned char odt_cfg, mode_odt_enable;
153 unsigned int max_bus_clk;
154 unsigned int max_data_rate, effective_data_rate;
155 unsigned int ddrc_clk;
156 unsigned int refresh_clk;
157 unsigned int sdram_cfg;
158 unsigned int ddrc_ecc_enable;
159 unsigned int pvr = get_pvr();
160
161 /*
162 * First disable the memory controller (could be enabled
163 * by the debugger)
164 */
165 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
166 sync();
167 isync();
168
169 /* Read SPD parameters with I2C */
170 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
171 SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
172 #ifdef SPD_DEBUG
173 spd_debug(&spd);
174 #endif
175 /* Check the memory type */
176 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
177 debug("DDR: Module mem type is %02X\n", spd.mem_type);
178 return 0;
179 }
180
181 /* Check the number of physical bank */
182 if (spd.mem_type == SPD_MEMTYPE_DDR) {
183 n_ranks = spd.nrows;
184 } else {
185 n_ranks = (spd.nrows & 0x7) + 1;
186 }
187
188 if (n_ranks > 2) {
189 printf("DDR: The number of physical bank is %02X\n", n_ranks);
190 return 0;
191 }
192
193 /* Check if the number of row of the module is in the range of DDRC */
194 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
195 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
196 spd.nrow_addr);
197 return 0;
198 }
199
200 /* Check if the number of col of the module is in the range of DDRC */
201 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
202 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
203 spd.ncol_addr);
204 return 0;
205 }
206
207 #ifdef CONFIG_SYS_DDRCDR_VALUE
208 /*
209 * Adjust DDR II IO voltage biasing. It just makes it work.
210 */
211 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
212 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
213 }
214 udelay(50000);
215 #endif
216
217 /*
218 * ODT configuration recommendation from DDR Controller Chapter.
219 */
220 odt_rd_cfg = 0; /* Never assert ODT */
221 odt_wr_cfg = 0; /* Never assert ODT */
222 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
223 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
224 }
225
226 /* Setup DDR chip select register */
227 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
228 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
229 ddr->cs_config[0] = ( 1 << 31
230 | (odt_rd_cfg << 20)
231 | (odt_wr_cfg << 16)
232 | ((spd.nbanks == 8 ? 1 : 0) << 14)
233 | ((spd.nrow_addr - 12) << 8)
234 | (spd.ncol_addr - 8) );
235 debug("\n");
236 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
237 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
238
239 if (n_ranks == 2) {
240 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
241 | ((banksize(spd.row_dens) >> 23) - 1) );
242 ddr->cs_config[1] = ( 1<<31
243 | (odt_rd_cfg << 20)
244 | (odt_wr_cfg << 16)
245 | ((spd.nbanks == 8 ? 1 : 0) << 14)
246 | ((spd.nrow_addr - 12) << 8)
247 | (spd.ncol_addr - 8) );
248 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
249 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
250 }
251
252 #else
253 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
254 ddr->cs_config[2] = ( 1 << 31
255 | (odt_rd_cfg << 20)
256 | (odt_wr_cfg << 16)
257 | ((spd.nbanks == 8 ? 1 : 0) << 14)
258 | ((spd.nrow_addr - 12) << 8)
259 | (spd.ncol_addr - 8) );
260 debug("\n");
261 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
262 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
263
264 if (n_ranks == 2) {
265 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
266 | ((banksize(spd.row_dens) >> 23) - 1) );
267 ddr->cs_config[3] = ( 1<<31
268 | (odt_rd_cfg << 20)
269 | (odt_wr_cfg << 16)
270 | ((spd.nbanks == 8 ? 1 : 0) << 14)
271 | ((spd.nrow_addr - 12) << 8)
272 | (spd.ncol_addr - 8) );
273 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
274 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
275 }
276 #endif
277
278 /*
279 * Figure out memory size in Megabytes.
280 */
281 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
282
283 /*
284 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
285 */
286 law_size = 19 + __ilog2(memsize);
287
288 /*
289 * Set up LAWBAR for all of DDR.
290 */
291 ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
292 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
293 debug("DDR:bar=0x%08x\n", ecm->bar);
294 debug("DDR:ar=0x%08x\n", ecm->ar);
295
296 /*
297 * Find the largest CAS by locating the highest 1 bit
298 * in the spd.cas_lat field. Translate it to a DDR
299 * controller field value:
300 *
301 * CAS Lat DDR I DDR II Ctrl
302 * Clocks SPD Bit SPD Bit Value
303 * ------- ------- ------- -----
304 * 1.0 0 0001
305 * 1.5 1 0010
306 * 2.0 2 2 0011
307 * 2.5 3 0100
308 * 3.0 4 3 0101
309 * 3.5 5 0110
310 * 4.0 6 4 0111
311 * 4.5 1000
312 * 5.0 5 1001
313 */
314 caslat = __ilog2(spd.cas_lat);
315 if ((spd.mem_type == SPD_MEMTYPE_DDR)
316 && (caslat > 6)) {
317 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
318 return 0;
319 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
320 && (caslat < 2 || caslat > 5)) {
321 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
322 spd.cas_lat);
323 return 0;
324 }
325 debug("DDR: caslat SPD bit is %d\n", caslat);
326
327 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
328 + (spd.clk_cycle & 0x0f));
329 max_data_rate = max_bus_clk * 2;
330
331 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
332
333 ddrc_clk = gd->mem_clk / 1000000;
334 effective_data_rate = 0;
335
336 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
337 if (spd.cas_lat & 0x08)
338 caslat = 3;
339 else
340 caslat = 4;
341 if (ddrc_clk <= 460 && ddrc_clk > 350)
342 effective_data_rate = 400;
343 else if (ddrc_clk <=350 && ddrc_clk > 280)
344 effective_data_rate = 333;
345 else if (ddrc_clk <= 280 && ddrc_clk > 230)
346 effective_data_rate = 266;
347 else
348 effective_data_rate = 200;
349 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
350 if (ddrc_clk <= 460 && ddrc_clk > 350) {
351 /* DDR controller clk at 350~460 */
352 effective_data_rate = 400; /* 5ns */
353 caslat = caslat;
354 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
355 /* DDR controller clk at 280~350 */
356 effective_data_rate = 333; /* 6ns */
357 if (spd.clk_cycle2 == 0x60)
358 caslat = caslat - 1;
359 else
360 caslat = caslat;
361 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
362 /* DDR controller clk at 230~280 */
363 effective_data_rate = 266; /* 7.5ns */
364 if (spd.clk_cycle3 == 0x75)
365 caslat = caslat - 2;
366 else if (spd.clk_cycle2 == 0x75)
367 caslat = caslat - 1;
368 else
369 caslat = caslat;
370 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
371 /* DDR controller clk at 90~230 */
372 effective_data_rate = 200; /* 10ns */
373 if (spd.clk_cycle3 == 0xa0)
374 caslat = caslat - 2;
375 else if (spd.clk_cycle2 == 0xa0)
376 caslat = caslat - 1;
377 else
378 caslat = caslat;
379 }
380 } else if (max_data_rate >= 323) { /* it is DDR 333 */
381 if (ddrc_clk <= 350 && ddrc_clk > 280) {
382 /* DDR controller clk at 280~350 */
383 effective_data_rate = 333; /* 6ns */
384 caslat = caslat;
385 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
386 /* DDR controller clk at 230~280 */
387 effective_data_rate = 266; /* 7.5ns */
388 if (spd.clk_cycle2 == 0x75)
389 caslat = caslat - 1;
390 else
391 caslat = caslat;
392 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
393 /* DDR controller clk at 90~230 */
394 effective_data_rate = 200; /* 10ns */
395 if (spd.clk_cycle3 == 0xa0)
396 caslat = caslat - 2;
397 else if (spd.clk_cycle2 == 0xa0)
398 caslat = caslat - 1;
399 else
400 caslat = caslat;
401 }
402 } else if (max_data_rate >= 256) { /* it is DDR 266 */
403 if (ddrc_clk <= 350 && ddrc_clk > 280) {
404 /* DDR controller clk at 280~350 */
405 printf("DDR: DDR controller freq is more than "
406 "max data rate of the module\n");
407 return 0;
408 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
409 /* DDR controller clk at 230~280 */
410 effective_data_rate = 266; /* 7.5ns */
411 caslat = caslat;
412 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
413 /* DDR controller clk at 90~230 */
414 effective_data_rate = 200; /* 10ns */
415 if (spd.clk_cycle2 == 0xa0)
416 caslat = caslat - 1;
417 }
418 } else if (max_data_rate >= 190) { /* it is DDR 200 */
419 if (ddrc_clk <= 350 && ddrc_clk > 230) {
420 /* DDR controller clk at 230~350 */
421 printf("DDR: DDR controller freq is more than "
422 "max data rate of the module\n");
423 return 0;
424 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
425 /* DDR controller clk at 90~230 */
426 effective_data_rate = 200; /* 10ns */
427 caslat = caslat;
428 }
429 }
430
431 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
432 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
433
434 /*
435 * Errata DDR6 work around: input enable 2 cycles earlier.
436 * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
437 */
438 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
439 if (caslat == 2)
440 ddr->debug_reg = 0x201c0000; /* CL=2 */
441 else if (caslat == 3)
442 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
443 else if (caslat == 4)
444 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
445
446 sync();
447
448 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
449 }
450
451 /*
452 * Convert caslat clocks to DDR controller value.
453 * Force caslat_ctrl to be DDR Controller field-sized.
454 */
455 if (spd.mem_type == SPD_MEMTYPE_DDR) {
456 caslat_ctrl = (caslat + 1) & 0x07;
457 } else {
458 caslat_ctrl = (2 * caslat - 1) & 0x0f;
459 }
460
461 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
462 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
463 caslat, caslat_ctrl);
464
465 /*
466 * Timing Config 0.
467 * Avoid writing for DDR I.
468 */
469 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
470 unsigned char taxpd_clk = 8; /* By the book. */
471 unsigned char tmrd_clk = 2; /* By the book. */
472 unsigned char act_pd_exit = 2; /* Empirical? */
473 unsigned char pre_pd_exit = 6; /* Empirical? */
474
475 ddr->timing_cfg_0 = (0
476 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
477 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
478 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
479 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
480 );
481 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
482 }
483
484 /*
485 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
486 * use conservative value.
487 * For DDR II, they are bytes 36 and 37, in quarter nanos.
488 */
489
490 if (spd.mem_type == SPD_MEMTYPE_DDR) {
491 twr_clk = 3; /* Clocks */
492 twtr_clk = 1; /* Clocks */
493 } else {
494 twr_clk = picos_to_clk(spd.twr * 250);
495 twtr_clk = picos_to_clk(spd.twtr * 250);
496 if (twtr_clk < 2)
497 twtr_clk = 2;
498 }
499
500 /*
501 * Calculate Trfc, in picos.
502 * DDR I: Byte 42 straight up in ns.
503 * DDR II: Byte 40 and 42 swizzled some, in ns.
504 */
505 if (spd.mem_type == SPD_MEMTYPE_DDR) {
506 trfc = spd.trfc * 1000; /* up to ps */
507 } else {
508 unsigned int byte40_table_ps[8] = {
509 0,
510 250,
511 330,
512 500,
513 660,
514 750,
515 0,
516 0
517 };
518
519 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
520 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
521 }
522 trfc_clk = picos_to_clk(trfc);
523
524 /*
525 * Trcd, Byte 29, from quarter nanos to ps and clocks.
526 */
527 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
528
529 /*
530 * Convert trfc_clk to DDR controller fields. DDR I should
531 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
532 * 83xx controller has an extended REFREC field of three bits.
533 * The controller automatically adds 8 clocks to this value,
534 * so preadjust it down 8 first before splitting it up.
535 */
536 trfc_low = (trfc_clk - 8) & 0xf;
537
538 ddr->timing_cfg_1 =
539 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
540 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
541 (trcd_clk << 20 ) | /* ACTTORW */
542 (caslat_ctrl << 16 ) | /* CASLAT */
543 (trfc_low << 12 ) | /* REFEC */
544 ((twr_clk & 0x07) << 8) | /* WRRREC */
545 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
546 ((twtr_clk & 0x07) << 0) /* WRTORD */
547 );
548
549 /*
550 * Additive Latency
551 * For DDR I, 0.
552 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
553 * which comes from Trcd, and also note that:
554 * add_lat + caslat must be >= 4
555 */
556 add_lat = 0;
557 if (spd.mem_type == SPD_MEMTYPE_DDR2
558 && (odt_wr_cfg || odt_rd_cfg)
559 && (caslat < 4)) {
560 add_lat = 4 - caslat;
561 if ((add_lat + caslat) < 4) {
562 add_lat = 0;
563 }
564 }
565
566 /*
567 * Write Data Delay
568 * Historically 0x2 == 4/8 clock delay.
569 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
570 */
571 wr_data_delay = 2;
572 #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
573 wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
574 #endif
575
576 /*
577 * Write Latency
578 * Read to Precharge
579 * Minimum CKE Pulse Width.
580 * Four Activate Window
581 */
582 if (spd.mem_type == SPD_MEMTYPE_DDR) {
583 /*
584 * This is a lie. It should really be 1, but if it is
585 * set to 1, bits overlap into the old controller's
586 * otherwise unused ACSM field. If we leave it 0, then
587 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
588 */
589 wr_lat = 0;
590
591 trtp_clk = 2; /* By the book. */
592 cke_min_clk = 1; /* By the book. */
593 four_act = 1; /* By the book. */
594
595 } else {
596 wr_lat = caslat - 1;
597
598 /* Convert SPD value from quarter nanos to picos. */
599 trtp_clk = picos_to_clk(spd.trtp * 250);
600 if (trtp_clk < 2)
601 trtp_clk = 2;
602 trtp_clk += add_lat;
603
604 cke_min_clk = 3; /* By the book. */
605 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
606 }
607
608 /*
609 * Empirically set ~MCAS-to-preamble override for DDR 2.
610 * Your mileage will vary.
611 */
612 cpo = 0;
613 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
614 #ifdef CONFIG_SYS_DDR_CPO
615 cpo = CONFIG_SYS_DDR_CPO;
616 #else
617 if (effective_data_rate == 266) {
618 cpo = 0x4; /* READ_LAT + 1/2 */
619 } else if (effective_data_rate == 333) {
620 cpo = 0x6; /* READ_LAT + 1 */
621 } else if (effective_data_rate == 400) {
622 cpo = 0x7; /* READ_LAT + 5/4 */
623 } else {
624 /* Automatic calibration */
625 cpo = 0x1f;
626 }
627 #endif
628 }
629
630 ddr->timing_cfg_2 = (0
631 | ((add_lat & 0x7) << 28) /* ADD_LAT */
632 | ((cpo & 0x1f) << 23) /* CPO */
633 | ((wr_lat & 0x7) << 19) /* WR_LAT */
634 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
635 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
636 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
637 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
638 );
639
640 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
641 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
642
643 /* Check DIMM data bus width */
644 if (spd.dataw_lsb < 64) {
645 if (spd.mem_type == SPD_MEMTYPE_DDR)
646 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
647 else
648 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
649 debug("\n DDR DIMM: data bus width is 32 bit");
650 } else {
651 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
652 debug("\n DDR DIMM: data bus width is 64 bit");
653 }
654
655 /* Is this an ECC DDR chip? */
656 if (spd.config == 0x02)
657 debug(" with ECC\n");
658 else
659 debug(" without ECC\n");
660
661 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
662 Burst type is sequential
663 */
664 if (spd.mem_type == SPD_MEMTYPE_DDR) {
665 switch (caslat) {
666 case 1:
667 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
668 break;
669 case 2:
670 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
671 break;
672 case 3:
673 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
674 break;
675 case 4:
676 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
677 break;
678 default:
679 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
680 return 0;
681 }
682 } else {
683 mode_odt_enable = 0x0; /* Default disabled */
684 if (odt_wr_cfg || odt_rd_cfg) {
685 /*
686 * Bits 6 and 2 in Extended MRS(1)
687 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
688 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
689 */
690 mode_odt_enable = 0x40; /* 150 Ohm */
691 }
692
693 ddr->sdram_mode =
694 (0
695 | (1 << (16 + 10)) /* DQS Differential disable */
696 #ifdef CONFIG_SYS_DDR_MODE_WEAK
697 | (1 << (16 + 1)) /* weak driver (~60%) */
698 #endif
699 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
700 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
701 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
702 | (caslat << 4) /* caslat */
703 | (burstlen << 0) /* Burst length */
704 );
705 }
706 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
707
708 /*
709 * Clear EMRS2 and EMRS3.
710 */
711 ddr->sdram_mode2 = 0;
712 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
713
714 switch (spd.refresh) {
715 case 0x00:
716 case 0x80:
717 refresh_clk = picos_to_clk(15625000);
718 break;
719 case 0x01:
720 case 0x81:
721 refresh_clk = picos_to_clk(3900000);
722 break;
723 case 0x02:
724 case 0x82:
725 refresh_clk = picos_to_clk(7800000);
726 break;
727 case 0x03:
728 case 0x83:
729 refresh_clk = picos_to_clk(31300000);
730 break;
731 case 0x04:
732 case 0x84:
733 refresh_clk = picos_to_clk(62500000);
734 break;
735 case 0x05:
736 case 0x85:
737 refresh_clk = picos_to_clk(125000000);
738 break;
739 default:
740 refresh_clk = 0x512;
741 break;
742 }
743
744 /*
745 * Set BSTOPRE to 0x100 for page mode
746 * If auto-charge is used, set BSTOPRE = 0
747 */
748 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
749 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
750
751 /*
752 * SDRAM Cfg 2
753 */
754 odt_cfg = 0;
755 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
756 if (odt_rd_cfg | odt_wr_cfg) {
757 odt_cfg = 0x2; /* ODT to IOs during reads */
758 }
759 #endif
760 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
761 ddr->sdram_cfg2 = (0
762 | (0 << 26) /* True DQS */
763 | (odt_cfg << 21) /* ODT only read */
764 | (1 << 12) /* 1 refresh at a time */
765 );
766
767 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
768 }
769
770 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
771 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
772 #endif
773 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
774
775 sync();
776 isync();
777
778 udelay(600);
779
780 /*
781 * Figure out the settings for the sdram_cfg register. Build up
782 * the value in 'sdram_cfg' before writing since the write into
783 * the register will actually enable the memory controller, and all
784 * settings must be done before enabling.
785 *
786 * sdram_cfg[0] = 1 (ddr sdram logic enable)
787 * sdram_cfg[1] = 1 (self-refresh-enable)
788 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
789 * 010 DDR 1 SDRAM
790 * 011 DDR 2 SDRAM
791 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
792 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
793 */
794 if (spd.mem_type == SPD_MEMTYPE_DDR)
795 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
796 else
797 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
798
799 sdram_cfg = (0
800 | SDRAM_CFG_MEM_EN /* DDR enable */
801 | SDRAM_CFG_SREN /* Self refresh */
802 | sdram_type /* SDRAM type */
803 );
804
805 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
806 if (spd.mod_attr & 0x02)
807 sdram_cfg |= SDRAM_CFG_RD_EN;
808
809 /* The DIMM is 32bit width */
810 if (spd.dataw_lsb < 64) {
811 if (spd.mem_type == SPD_MEMTYPE_DDR)
812 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
813 if (spd.mem_type == SPD_MEMTYPE_DDR2)
814 sdram_cfg |= SDRAM_CFG_32_BE;
815 }
816
817 ddrc_ecc_enable = 0;
818
819 #if defined(CONFIG_DDR_ECC)
820 /* Enable ECC with sdram_cfg[2] */
821 if (spd.config == 0x02) {
822 sdram_cfg |= 0x20000000;
823 ddrc_ecc_enable = 1;
824 /* disable error detection */
825 ddr->err_disable = ~ECC_ERROR_ENABLE;
826 /* set single bit error threshold to maximum value,
827 * reset counter to zero */
828 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
829 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
830 }
831
832 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
833 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
834 #endif
835 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
836
837 #if defined(CONFIG_DDR_2T_TIMING)
838 /*
839 * Enable 2T timing by setting sdram_cfg[16].
840 */
841 sdram_cfg |= SDRAM_CFG_2T_EN;
842 #endif
843 /* Enable controller, and GO! */
844 ddr->sdram_cfg = sdram_cfg;
845 sync();
846 isync();
847 udelay(500);
848
849 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
850 return memsize; /*in MBytes*/
851 }
852 #endif /* CONFIG_SPD_EEPROM */
853
854 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
mftbu(void)855 static inline u32 mftbu(void)
856 {
857 u32 rval;
858
859 asm volatile("mftbu %0" : "=r" (rval));
860 return rval;
861 }
862
mftb(void)863 static inline u32 mftb(void)
864 {
865 u32 rval;
866
867 asm volatile("mftb %0" : "=r" (rval));
868 return rval;
869 }
870
871 /*
872 * Use timebase counter, get_timer() is not available
873 * at this point of initialization yet.
874 */
get_tbms(void)875 static __inline__ unsigned long get_tbms (void)
876 {
877 unsigned long tbl;
878 unsigned long tbu1, tbu2;
879 unsigned long ms;
880 unsigned long long tmp;
881
882 ulong tbclk = get_tbclk();
883
884 /* get the timebase ticks */
885 do {
886 tbu1 = mftbu();
887 tbl = mftb();
888 tbu2 = mftbu();
889 } while (tbu1 != tbu2);
890
891 /* convert ticks to ms */
892 tmp = (unsigned long long)(tbu1);
893 tmp = (tmp << 32);
894 tmp += (unsigned long long)(tbl);
895 ms = tmp/(tbclk/1000);
896
897 return ms;
898 }
899
900 /*
901 * Initialize all of memory for ECC, then enable errors.
902 */
ddr_enable_ecc(unsigned int dram_size)903 void ddr_enable_ecc(unsigned int dram_size)
904 {
905 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
906 volatile ddr83xx_t *ddr= &immap->ddr;
907 unsigned long t_start, t_end;
908 register u64 *p;
909 register uint size;
910 unsigned int pattern[2];
911
912 icache_enable();
913 t_start = get_tbms();
914 pattern[0] = 0xdeadbeef;
915 pattern[1] = 0xdeadbeef;
916
917 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
918 dma_meminit(pattern[0], dram_size);
919 #else
920 debug("ddr init: CPU FP write method\n");
921 size = dram_size;
922 for (p = 0; p < (u64*)(size); p++) {
923 ppcDWstore((u32*)p, pattern);
924 }
925 sync();
926 #endif
927
928 t_end = get_tbms();
929 icache_disable();
930
931 debug("\nREADY!!\n");
932 debug("ddr init duration: %ld ms\n", t_end - t_start);
933
934 /* Clear All ECC Errors */
935 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
936 ddr->err_detect |= ECC_ERROR_DETECT_MME;
937 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
938 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
939 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
940 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
941 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
942 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
943
944 /* Disable ECC-Interrupts */
945 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
946
947 /* Enable errors for ECC */
948 ddr->err_disable &= ECC_ERROR_ENABLE;
949
950 sync();
951 isync();
952 }
953 #endif /* CONFIG_DDR_ECC */
954
955 #endif /* !CONFIG_MPC83XX_SDRAM */
956