1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 STMicroelectronics R&D Limited
4 */
5#include <dt-bindings/clock/stih407-clks.h>
6/ {
7	/*
8	 * Fixed 30MHz oscillator inputs to SoC
9	 */
10	clk_sysin: clk-sysin {
11		#clock-cells = <0>;
12		compatible = "fixed-clock";
13		clock-frequency = <30000000>;
14	};
15
16	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
17		#clock-cells = <0>;
18		compatible = "fixed-clock";
19		clock-frequency = <0>;
20	};
21
22	clocks {
23		#address-cells = <1>;
24		#size-cells = <1>;
25		ranges;
26
27		/*
28		 * A9 PLL.
29		 */
30		clockgen-a9@92b0000 {
31			compatible = "st,clkgen-c32";
32			reg = <0x92b0000 0xffff>;
33
34			clockgen_a9_pll: clockgen-a9-pll {
35				#clock-cells = <1>;
36				compatible = "st,stih407-clkgen-plla9";
37
38				clocks = <&clk_sysin>;
39			};
40		};
41
42		/*
43		 * ARM CPU related clocks.
44		 */
45		clk_m_a9: clk-m-a9@92b0000 {
46			#clock-cells = <0>;
47			compatible = "st,stih407-clkgen-a9-mux";
48			reg = <0x92b0000 0x10000>;
49
50			clocks = <&clockgen_a9_pll 0>,
51				 <&clockgen_a9_pll 0>,
52				 <&clk_s_c0_flexgen 13>,
53				 <&clk_m_a9_ext2f_div2>;
54
55
56			/*
57			 * ARM Peripheral clock for timers
58			 */
59			arm_periph_clk: clk-m-a9-periphs {
60				#clock-cells = <0>;
61				compatible = "fixed-factor-clock";
62
63				clocks = <&clk_m_a9>;
64				clock-div = <2>;
65				clock-mult = <1>;
66			};
67		};
68
69		clockgen-a@90ff000 {
70			compatible = "st,clkgen-c32";
71			reg = <0x90ff000 0x1000>;
72
73			clk_s_a0_pll: clk-s-a0-pll {
74				#clock-cells = <1>;
75				compatible = "st,clkgen-pll0-a0";
76
77				clocks = <&clk_sysin>;
78			};
79
80			clk_s_a0_flexgen: clk-s-a0-flexgen {
81				compatible = "st,flexgen", "st,flexgen-stih407-a0";
82
83				#clock-cells = <1>;
84
85				clocks = <&clk_s_a0_pll 0>,
86					 <&clk_sysin>;
87			};
88		};
89
90		clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
91			#clock-cells = <1>;
92			compatible = "st,quadfs-pll";
93			reg = <0x9103000 0x1000>;
94
95			clocks = <&clk_sysin>;
96		};
97
98		clk_s_c0: clockgen-c@9103000 {
99			compatible = "st,clkgen-c32";
100			reg = <0x9103000 0x1000>;
101
102			clk_s_c0_pll0: clk-s-c0-pll0 {
103				#clock-cells = <1>;
104				compatible = "st,clkgen-pll0-c0";
105
106				clocks = <&clk_sysin>;
107			};
108
109			clk_s_c0_pll1: clk-s-c0-pll1 {
110				#clock-cells = <1>;
111				compatible = "st,clkgen-pll1-c0";
112
113				clocks = <&clk_sysin>;
114			};
115
116			clk_s_c0_flexgen: clk-s-c0-flexgen {
117				#clock-cells = <1>;
118				compatible = "st,flexgen", "st,flexgen-stih407-c0";
119
120				clocks = <&clk_s_c0_pll0 0>,
121					 <&clk_s_c0_pll1 0>,
122					 <&clk_s_c0_quadfs 0>,
123					 <&clk_s_c0_quadfs 1>,
124					 <&clk_s_c0_quadfs 2>,
125					 <&clk_s_c0_quadfs 3>,
126					 <&clk_sysin>;
127
128				/*
129				 * ARM Peripheral clock for timers
130				 */
131				clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
132					#clock-cells = <0>;
133					compatible = "fixed-factor-clock";
134
135					clocks = <&clk_s_c0_flexgen 13>;
136
137					clock-output-names = "clk-m-a9-ext2f-div2";
138
139					clock-div = <2>;
140					clock-mult = <1>;
141				};
142			};
143		};
144
145		clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
146			#clock-cells = <1>;
147			compatible = "st,quadfs-d0";
148			reg = <0x9104000 0x1000>;
149
150			clocks = <&clk_sysin>;
151		};
152
153		clockgen-d0@9104000 {
154			compatible = "st,clkgen-c32";
155			reg = <0x9104000 0x1000>;
156
157			clk_s_d0_flexgen: clk-s-d0-flexgen {
158				#clock-cells = <1>;
159				compatible = "st,flexgen", "st,flexgen-stih407-d0";
160
161				clocks = <&clk_s_d0_quadfs 0>,
162					 <&clk_s_d0_quadfs 1>,
163					 <&clk_s_d0_quadfs 2>,
164					 <&clk_s_d0_quadfs 3>,
165					 <&clk_sysin>;
166			};
167		};
168
169		clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
170			#clock-cells = <1>;
171			compatible = "st,quadfs-d2";
172			reg = <0x9106000 0x1000>;
173
174			clocks = <&clk_sysin>;
175		};
176
177		clockgen-d2@9106000 {
178			compatible = "st,clkgen-c32";
179			reg = <0x9106000 0x1000>;
180
181			clk_s_d2_flexgen: clk-s-d2-flexgen {
182				#clock-cells = <1>;
183				compatible = "st,flexgen", "st,flexgen-stih407-d2";
184
185				clocks = <&clk_s_d2_quadfs 0>,
186					 <&clk_s_d2_quadfs 1>,
187					 <&clk_s_d2_quadfs 2>,
188					 <&clk_s_d2_quadfs 3>,
189					 <&clk_sysin>,
190					 <&clk_sysin>,
191					 <&clk_tmdsout_hdmi>;
192			};
193		};
194
195		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
196			#clock-cells = <1>;
197			compatible = "st,quadfs-d3";
198			reg = <0x9107000 0x1000>;
199
200			clocks = <&clk_sysin>;
201		};
202
203		clockgen-d3@9107000 {
204			compatible = "st,clkgen-c32";
205			reg = <0x9107000 0x1000>;
206
207			clk_s_d3_flexgen: clk-s-d3-flexgen {
208				#clock-cells = <1>;
209				compatible = "st,flexgen", "st,flexgen-stih407-d3";
210
211				clocks = <&clk_s_d3_quadfs 0>,
212					 <&clk_s_d3_quadfs 1>,
213					 <&clk_s_d3_quadfs 2>,
214					 <&clk_s_d3_quadfs 3>,
215					 <&clk_sysin>;
216			};
217		};
218	};
219};
220