1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014 STMicroelectronics Limited. 4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 5 */ 6#include "stih407-pinctrl.dtsi" 7#include <dt-bindings/mfd/st-lpc.h> 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/reset/stih407-resets.h> 10#include <dt-bindings/interrupt-controller/irq-st.h> 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 reserved-memory { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 ranges; 19 20 gp0_reserved: rproc@45000000 { 21 compatible = "shared-dma-pool"; 22 reg = <0x45000000 0x00400000>; 23 no-map; 24 }; 25 26 delta_reserved: rproc@44000000 { 27 compatible = "shared-dma-pool"; 28 reg = <0x44000000 0x01000000>; 29 no-map; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a9"; 39 reg = <0>; 40 41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 42 cpu-release-addr = <0x94100A4>; 43 44 /* kHz uV */ 45 operating-points = <1500000 0 46 1200000 0 47 800000 0 48 500000 0>; 49 50 clocks = <&clk_m_a9>; 51 clock-names = "cpu"; 52 clock-latency = <100000>; 53 cpu0-supply = <&pwm_regulator>; 54 st,syscfg = <&syscfg_core 0x8e0>; 55 }; 56 cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a9"; 59 reg = <1>; 60 61 /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 62 cpu-release-addr = <0x94100A4>; 63 64 /* kHz uV */ 65 operating-points = <1500000 0 66 1200000 0 67 800000 0 68 500000 0>; 69 }; 70 }; 71 72 intc: interrupt-controller@8761000 { 73 compatible = "arm,cortex-a9-gic"; 74 #interrupt-cells = <3>; 75 interrupt-controller; 76 reg = <0x08761000 0x1000>, <0x08760100 0x100>; 77 }; 78 79 scu@8760000 { 80 compatible = "arm,cortex-a9-scu"; 81 reg = <0x08760000 0x1000>; 82 }; 83 84 timer@8760200 { 85 interrupt-parent = <&intc>; 86 compatible = "arm,cortex-a9-global-timer"; 87 reg = <0x08760200 0x100>; 88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&arm_periph_clk>; 90 }; 91 92 l2: cache-controller@8762000 { 93 compatible = "arm,pl310-cache"; 94 reg = <0x08762000 0x1000>; 95 arm,data-latency = <3 3 3>; 96 arm,tag-latency = <2 2 2>; 97 cache-unified; 98 cache-level = <2>; 99 }; 100 101 arm-pmu { 102 interrupt-parent = <&intc>; 103 compatible = "arm,cortex-a9-pmu"; 104 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 pwm_regulator: pwm-regulator { 108 compatible = "pwm-regulator"; 109 pwms = <&pwm1 3 8448>; 110 regulator-name = "CPU_1V0_AVS"; 111 regulator-min-microvolt = <784000>; 112 regulator-max-microvolt = <1299000>; 113 regulator-always-on; 114 max-duty-cycle = <255>; 115 status = "okay"; 116 }; 117 118 soc { 119 #address-cells = <1>; 120 #size-cells = <1>; 121 interrupt-parent = <&intc>; 122 ranges; 123 compatible = "simple-bus"; 124 125 restart: restart-controller@0 { 126 compatible = "st,stih407-restart"; 127 reg = <0 0>; 128 st,syscfg = <&syscfg_sbc_reg>; 129 status = "okay"; 130 }; 131 132 powerdown: powerdown-controller@0 { 133 compatible = "st,stih407-powerdown"; 134 reg = <0 0>; 135 #reset-cells = <1>; 136 }; 137 138 softreset: softreset-controller@0 { 139 compatible = "st,stih407-softreset"; 140 reg = <0 0>; 141 #reset-cells = <1>; 142 }; 143 144 picophyreset: picophyreset-controller@0 { 145 compatible = "st,stih407-picophyreset"; 146 reg = <0 0>; 147 #reset-cells = <1>; 148 }; 149 150 syscfg_sbc: sbc-syscfg@9620000 { 151 compatible = "st,stih407-sbc-syscfg", "syscon"; 152 reg = <0x9620000 0x1000>; 153 }; 154 155 syscfg_front: front-syscfg@9280000 { 156 compatible = "st,stih407-front-syscfg", "syscon"; 157 reg = <0x9280000 0x1000>; 158 }; 159 160 syscfg_rear: rear-syscfg@9290000 { 161 compatible = "st,stih407-rear-syscfg", "syscon"; 162 reg = <0x9290000 0x1000>; 163 }; 164 165 syscfg_flash: flash-syscfg@92a0000 { 166 compatible = "st,stih407-flash-syscfg", "syscon"; 167 reg = <0x92a0000 0x1000>; 168 }; 169 170 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { 171 compatible = "st,stih407-sbc-reg-syscfg", "syscon"; 172 reg = <0x9600000 0x1000>; 173 }; 174 175 syscfg_core: core-syscfg@92b0000 { 176 compatible = "st,stih407-core-syscfg", "syscon"; 177 reg = <0x92b0000 0x1000>; 178 179 sti_sasg_codec: sti-sasg-codec { 180 compatible = "st,stih407-sas-codec"; 181 #sound-dai-cells = <1>; 182 status = "disabled"; 183 st,syscfg = <&syscfg_core>; 184 }; 185 }; 186 187 syscfg_lpm: lpm-syscfg@94b5100 { 188 compatible = "st,stih407-lpm-syscfg", "syscon"; 189 reg = <0x94b5100 0x1000>; 190 }; 191 192 irq-syscfg@0 { 193 compatible = "st,stih407-irq-syscfg"; 194 reg = <0 0>; 195 st,syscfg = <&syscfg_core>; 196 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 197 <ST_IRQ_SYSCFG_PMU_1>; 198 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 199 <ST_IRQ_SYSCFG_DISABLED>; 200 }; 201 202 /* Display */ 203 vtg_main: sti-vtg-main@8d02800 { 204 compatible = "st,vtg"; 205 reg = <0x8d02800 0x200>; 206 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 207 }; 208 209 vtg_aux: sti-vtg-aux@8d00200 { 210 compatible = "st,vtg"; 211 reg = <0x8d00200 0x100>; 212 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 213 }; 214 215 serial@9830000 { 216 compatible = "st,asc"; 217 reg = <0x9830000 0x2c>; 218 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 220 /* Pinctrl moved out to a per-board configuration */ 221 222 status = "disabled"; 223 }; 224 225 serial@9831000 { 226 compatible = "st,asc"; 227 reg = <0x9831000 0x2c>; 228 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_serial1>; 231 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 232 233 status = "disabled"; 234 }; 235 236 serial@9832000 { 237 compatible = "st,asc"; 238 reg = <0x9832000 0x2c>; 239 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_serial2>; 242 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 243 244 status = "disabled"; 245 }; 246 247 /* SBC_ASC0 - UART10 */ 248 sbc_serial0: serial@9530000 { 249 compatible = "st,asc"; 250 reg = <0x9530000 0x2c>; 251 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_sbc_serial0>; 254 clocks = <&clk_sysin>; 255 256 status = "disabled"; 257 }; 258 259 serial@9531000 { 260 compatible = "st,asc"; 261 reg = <0x9531000 0x2c>; 262 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_sbc_serial1>; 265 clocks = <&clk_sysin>; 266 267 status = "disabled"; 268 }; 269 270 i2c@9840000 { 271 compatible = "st,comms-ssc4-i2c"; 272 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 273 reg = <0x9840000 0x110>; 274 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 275 clock-names = "ssc"; 276 clock-frequency = <400000>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_i2c0_default>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 282 status = "disabled"; 283 }; 284 285 i2c@9841000 { 286 compatible = "st,comms-ssc4-i2c"; 287 reg = <0x9841000 0x110>; 288 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 290 clock-names = "ssc"; 291 clock-frequency = <400000>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_i2c1_default>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 status = "disabled"; 298 }; 299 300 i2c@9842000 { 301 compatible = "st,comms-ssc4-i2c"; 302 reg = <0x9842000 0x110>; 303 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 305 clock-names = "ssc"; 306 clock-frequency = <400000>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_i2c2_default>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 status = "disabled"; 313 }; 314 315 i2c@9843000 { 316 compatible = "st,comms-ssc4-i2c"; 317 reg = <0x9843000 0x110>; 318 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 320 clock-names = "ssc"; 321 clock-frequency = <400000>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_i2c3_default>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 status = "disabled"; 328 }; 329 330 i2c@9844000 { 331 compatible = "st,comms-ssc4-i2c"; 332 reg = <0x9844000 0x110>; 333 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 335 clock-names = "ssc"; 336 clock-frequency = <400000>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_i2c4_default>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 342 status = "disabled"; 343 }; 344 345 i2c@9845000 { 346 compatible = "st,comms-ssc4-i2c"; 347 reg = <0x9845000 0x110>; 348 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 350 clock-names = "ssc"; 351 clock-frequency = <400000>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_i2c5_default>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 357 status = "disabled"; 358 }; 359 360 361 /* SSCs on SBC */ 362 i2c@9540000 { 363 compatible = "st,comms-ssc4-i2c"; 364 reg = <0x9540000 0x110>; 365 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&clk_sysin>; 367 clock-names = "ssc"; 368 clock-frequency = <400000>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_i2c10_default>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 status = "disabled"; 375 }; 376 377 i2c@9541000 { 378 compatible = "st,comms-ssc4-i2c"; 379 reg = <0x9541000 0x110>; 380 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clk_sysin>; 382 clock-names = "ssc"; 383 clock-frequency = <400000>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_i2c11_default>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 389 status = "disabled"; 390 }; 391 392 usb2_picophy0: phy1@0 { 393 compatible = "st,stih407-usb2-phy"; 394 reg = <0 0>; 395 #phy-cells = <0>; 396 st,syscfg = <&syscfg_core 0x100 0xf4>; 397 resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 398 <&picophyreset STIH407_PICOPHY2_RESET>; 399 reset-names = "global", "port"; 400 }; 401 402 miphy28lp_phy: miphy28lp@0 { 403 compatible = "st,miphy28lp-phy"; 404 st,syscfg = <&syscfg_core>; 405 #address-cells = <1>; 406 #size-cells = <1>; 407 ranges; 408 reg = <0 0>; 409 410 phy_port0: port@9b22000 { 411 reg = <0x9b22000 0xff>, 412 <0x9b09000 0xff>, 413 <0x9b04000 0xff>; 414 reg-names = "sata-up", 415 "pcie-up", 416 "pipew"; 417 418 st,syscfg = <0x114 0x818 0xe0 0xec>; 419 #phy-cells = <1>; 420 421 reset-names = "miphy-sw-rst"; 422 resets = <&softreset STIH407_MIPHY0_SOFTRESET>; 423 }; 424 425 phy_port1: port@9b2a000 { 426 reg = <0x9b2a000 0xff>, 427 <0x9b19000 0xff>, 428 <0x9b14000 0xff>; 429 reg-names = "sata-up", 430 "pcie-up", 431 "pipew"; 432 433 st,syscfg = <0x118 0x81c 0xe4 0xf0>; 434 435 #phy-cells = <1>; 436 437 reset-names = "miphy-sw-rst"; 438 resets = <&softreset STIH407_MIPHY1_SOFTRESET>; 439 }; 440 441 phy_port2: port@8f95000 { 442 reg = <0x8f95000 0xff>, 443 <0x8f90000 0xff>; 444 reg-names = "pipew", 445 "usb3-up"; 446 447 st,syscfg = <0x11c 0x820>; 448 449 #phy-cells = <1>; 450 451 reset-names = "miphy-sw-rst"; 452 resets = <&softreset STIH407_MIPHY2_SOFTRESET>; 453 }; 454 }; 455 456 spi@9840000 { 457 compatible = "st,comms-ssc4-spi"; 458 reg = <0x9840000 0x110>; 459 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 461 clock-names = "ssc"; 462 pinctrl-0 = <&pinctrl_spi0_default>; 463 pinctrl-names = "default"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 467 status = "disabled"; 468 }; 469 470 spi@9841000 { 471 compatible = "st,comms-ssc4-spi"; 472 reg = <0x9841000 0x110>; 473 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 475 clock-names = "ssc"; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_spi1_default>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 481 status = "disabled"; 482 }; 483 484 spi@9842000 { 485 compatible = "st,comms-ssc4-spi"; 486 reg = <0x9842000 0x110>; 487 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 489 clock-names = "ssc"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pinctrl_spi2_default>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 495 status = "disabled"; 496 }; 497 498 spi@9843000 { 499 compatible = "st,comms-ssc4-spi"; 500 reg = <0x9843000 0x110>; 501 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 503 clock-names = "ssc"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_spi3_default>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 509 status = "disabled"; 510 }; 511 512 spi@9844000 { 513 compatible = "st,comms-ssc4-spi"; 514 reg = <0x9844000 0x110>; 515 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 517 clock-names = "ssc"; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_spi4_default>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 status = "disabled"; 524 }; 525 526 /* SBC SSC */ 527 spi@9540000 { 528 compatible = "st,comms-ssc4-spi"; 529 reg = <0x9540000 0x110>; 530 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clk_sysin>; 532 clock-names = "ssc"; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&pinctrl_spi10_default>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 538 status = "disabled"; 539 }; 540 541 spi@9541000 { 542 compatible = "st,comms-ssc4-spi"; 543 reg = <0x9541000 0x110>; 544 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clk_sysin>; 546 clock-names = "ssc"; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_spi11_default>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 552 status = "disabled"; 553 }; 554 555 spi@9542000 { 556 compatible = "st,comms-ssc4-spi"; 557 reg = <0x9542000 0x110>; 558 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&clk_sysin>; 560 clock-names = "ssc"; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_spi12_default>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 status = "disabled"; 567 }; 568 569 mmc0: sdhci@9060000 { 570 compatible = "st,sdhci-stih407", "st,sdhci"; 571 status = "disabled"; 572 reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 573 reg-names = "mmc", "top-mmc-delay"; 574 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 575 interrupt-names = "mmcirq"; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_mmc0>; 578 clock-names = "mmc", "icn"; 579 clocks = <&clk_s_c0_flexgen CLK_MMC_0>, 580 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 581 bus-width = <8>; 582 }; 583 584 mmc1: sdhci@9080000 { 585 compatible = "st,sdhci-stih407", "st,sdhci"; 586 status = "disabled"; 587 reg = <0x09080000 0x7ff>; 588 reg-names = "mmc"; 589 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "mmcirq"; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&pinctrl_sd1>; 593 clock-names = "mmc", "icn"; 594 clocks = <&clk_s_c0_flexgen CLK_MMC_1>, 595 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 596 resets = <&softreset STIH407_MMC1_SOFTRESET>; 597 bus-width = <4>; 598 }; 599 600 /* Watchdog and Real-Time Clock */ 601 lpc@8787000 { 602 compatible = "st,stih407-lpc"; 603 reg = <0x8787000 0x1000>; 604 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; 605 clocks = <&clk_s_d3_flexgen CLK_LPC_0>; 606 timeout-sec = <120>; 607 st,syscfg = <&syscfg_core>; 608 st,lpc-mode = <ST_LPC_MODE_WDT>; 609 }; 610 611 lpc@8788000 { 612 compatible = "st,stih407-lpc"; 613 reg = <0x8788000 0x1000>; 614 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; 615 clocks = <&clk_s_d3_flexgen CLK_LPC_1>; 616 st,lpc-mode = <ST_LPC_MODE_CLKSRC>; 617 }; 618 619 spifsm: spifsm@9022000{ 620 compatible = "st,spi-fsm"; 621 reg = <0x9022000 0x1000>; 622 reg-names = "spi-fsm"; 623 clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 624 clock-names = "emi_clk"; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&pinctrl_fsm>; 627 st,syscfg = <&syscfg_core>; 628 st,boot-device-reg = <0x8c4>; 629 st,boot-device-spi = <0x68>; 630 631 status = "disabled"; 632 }; 633 634 sata0: sata@9b20000 { 635 compatible = "st,ahci"; 636 reg = <0x9b20000 0x1000>; 637 638 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 639 interrupt-names = "hostc"; 640 641 phys = <&phy_port0 PHY_TYPE_SATA>; 642 phy-names = "ahci_phy"; 643 644 resets = <&powerdown STIH407_SATA0_POWERDOWN>, 645 <&softreset STIH407_SATA0_SOFTRESET>, 646 <&softreset STIH407_SATA0_PWR_SOFTRESET>; 647 reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; 648 649 clock-names = "ahci_clk"; 650 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 651 652 ports-implemented = <0x1>; 653 654 status = "disabled"; 655 }; 656 657 sata1: sata@9b28000 { 658 compatible = "st,ahci"; 659 reg = <0x9b28000 0x1000>; 660 661 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "hostc"; 663 664 phys = <&phy_port1 PHY_TYPE_SATA>; 665 phy-names = "ahci_phy"; 666 667 resets = <&powerdown STIH407_SATA1_POWERDOWN>, 668 <&softreset STIH407_SATA1_SOFTRESET>, 669 <&softreset STIH407_SATA1_PWR_SOFTRESET>; 670 reset-names = "pwr-dwn", 671 "sw-rst", 672 "pwr-rst"; 673 674 clock-names = "ahci_clk"; 675 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 676 677 ports-implemented = <0x1>; 678 679 status = "disabled"; 680 }; 681 682 683 st_dwc3: dwc3@8f94000 { 684 compatible = "st,stih407-dwc3"; 685 reg = <0x08f94000 0x1000>, <0x110 0x4>; 686 reg-names = "reg-glue", "syscfg-reg"; 687 st,syscfg = <&syscfg_core>; 688 resets = <&powerdown STIH407_USB3_POWERDOWN>, 689 <&softreset STIH407_MIPHY2_SOFTRESET>; 690 reset-names = "powerdown", "softreset"; 691 #address-cells = <1>; 692 #size-cells = <1>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_usb3>; 695 ranges; 696 697 status = "disabled"; 698 699 dwc3: dwc3@9900000 { 700 compatible = "snps,dwc3"; 701 reg = <0x09900000 0x100000>; 702 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 703 dr_mode = "host"; 704 phy-names = "usb2-phy", "usb3-phy"; 705 phys = <&usb2_picophy0>, 706 <&phy_port2 PHY_TYPE_USB3>; 707 snps,dis_u3_susphy_quirk; 708 }; 709 }; 710 711 /* COMMS PWM Module */ 712 pwm0: pwm@9810000 { 713 compatible = "st,sti-pwm"; 714 #pwm-cells = <2>; 715 reg = <0x9810000 0x68>; 716 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&pinctrl_pwm0_chan0_default>; 719 clock-names = "pwm"; 720 clocks = <&clk_sysin>; 721 st,pwm-num-chan = <1>; 722 723 status = "disabled"; 724 }; 725 726 /* SBC PWM Module */ 727 pwm1: pwm@9510000 { 728 compatible = "st,sti-pwm"; 729 #pwm-cells = <2>; 730 reg = <0x9510000 0x68>; 731 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_pwm1_chan0_default 734 &pinctrl_pwm1_chan1_default 735 &pinctrl_pwm1_chan2_default 736 &pinctrl_pwm1_chan3_default>; 737 clock-names = "pwm"; 738 clocks = <&clk_sysin>; 739 st,pwm-num-chan = <4>; 740 741 status = "disabled"; 742 }; 743 744 rng10: rng@8a89000 { 745 compatible = "st,rng"; 746 reg = <0x08a89000 0x1000>; 747 clocks = <&clk_sysin>; 748 status = "okay"; 749 }; 750 751 rng11: rng@8a8a000 { 752 compatible = "st,rng"; 753 reg = <0x08a8a000 0x1000>; 754 clocks = <&clk_sysin>; 755 status = "okay"; 756 }; 757 758 ethernet0: dwmac@9630000 { 759 device_type = "network"; 760 status = "disabled"; 761 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 762 reg = <0x9630000 0x8000>, <0x80 0x4>; 763 reg-names = "stmmaceth", "sti-ethconf"; 764 765 st,syscon = <&syscfg_sbc_reg 0x80>; 766 st,gmac_en; 767 resets = <&softreset STIH407_ETH1_SOFTRESET>; 768 reset-names = "stmmaceth"; 769 770 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 772 interrupt-names = "macirq", "eth_wake_irq"; 773 774 /* DMA Bus Mode */ 775 snps,pbl = <8>; 776 777 pinctrl-names = "default"; 778 pinctrl-0 = <&pinctrl_rgmii1>; 779 780 clock-names = "stmmaceth", "sti-ethclk"; 781 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, 782 <&clk_s_c0_flexgen CLK_ETH_PHY>; 783 }; 784 785 mailbox0: mailbox@8f00000 { 786 compatible = "st,stih407-mailbox"; 787 reg = <0x8f00000 0x1000>; 788 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 789 #mbox-cells = <2>; 790 mbox-name = "a9"; 791 status = "okay"; 792 }; 793 794 mailbox1: mailbox@8f01000 { 795 compatible = "st,stih407-mailbox"; 796 reg = <0x8f01000 0x1000>; 797 #mbox-cells = <2>; 798 mbox-name = "st231_gp_1"; 799 status = "okay"; 800 }; 801 802 mailbox2: mailbox@8f02000 { 803 compatible = "st,stih407-mailbox"; 804 reg = <0x8f02000 0x1000>; 805 #mbox-cells = <2>; 806 mbox-name = "st231_gp_0"; 807 status = "okay"; 808 }; 809 810 mailbox3: mailbox@8f03000 { 811 compatible = "st,stih407-mailbox"; 812 reg = <0x8f03000 0x1000>; 813 #mbox-cells = <2>; 814 mbox-name = "st231_audio_video"; 815 status = "okay"; 816 }; 817 818 st231_gp0: st231-gp0@0 { 819 compatible = "st,st231-rproc"; 820 reg = <0 0>; 821 memory-region = <&gp0_reserved>; 822 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; 823 reset-names = "sw_reset"; 824 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; 825 clock-frequency = <600000000>; 826 st,syscfg = <&syscfg_core 0x22c>; 827 #mbox-cells = <1>; 828 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 829 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; 830 }; 831 832 st231_delta: st231-delta@0 { 833 compatible = "st,st231-rproc"; 834 reg = <0 0>; 835 memory-region = <&delta_reserved>; 836 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; 837 reset-names = "sw_reset"; 838 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; 839 clock-frequency = <600000000>; 840 st,syscfg = <&syscfg_core 0x224>; 841 #mbox-cells = <1>; 842 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 843 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; 844 }; 845 846 /* fdma audio */ 847 fdma0: dma-controller@8e20000 { 848 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 849 reg = <0x8e20000 0x8000>, 850 <0x8e30000 0x3000>, 851 <0x8e37000 0x1000>, 852 <0x8e38000 0x8000>; 853 reg-names = "slimcore", "dmem", "peripherals", "imem"; 854 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 855 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 856 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 857 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 858 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 859 dma-channels = <16>; 860 #dma-cells = <3>; 861 }; 862 863 /* fdma app */ 864 fdma1: dma-controller@8e40000 { 865 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; 866 reg = <0x8e40000 0x8000>, 867 <0x8e50000 0x3000>, 868 <0x8e57000 0x1000>, 869 <0x8e58000 0x8000>; 870 reg-names = "slimcore", "dmem", "peripherals", "imem"; 871 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 872 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 873 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 874 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 875 876 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 877 dma-channels = <16>; 878 #dma-cells = <3>; 879 880 status = "disabled"; 881 }; 882 883 /* fdma free running */ 884 fdma2: dma-controller@8e60000 { 885 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; 886 reg = <0x8e60000 0x8000>, 887 <0x8e70000 0x3000>, 888 <0x8e77000 0x1000>, 889 <0x8e78000 0x8000>; 890 reg-names = "slimcore", "dmem", "peripherals", "imem"; 891 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 892 dma-channels = <16>; 893 #dma-cells = <3>; 894 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 895 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 896 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 897 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 898 899 status = "disabled"; 900 }; 901 902 sti_uni_player0: sti-uni-player@8d80000 { 903 compatible = "st,stih407-uni-player-hdmi"; 904 #sound-dai-cells = <0>; 905 st,syscfg = <&syscfg_core>; 906 clocks = <&clk_s_d0_flexgen CLK_PCM_0>; 907 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; 908 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; 909 assigned-clock-rates = <50000000>; 910 reg = <0x8d80000 0x158>; 911 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 912 dmas = <&fdma0 2 0 1>; 913 dma-names = "tx"; 914 915 status = "disabled"; 916 }; 917 918 sti_uni_player1: sti-uni-player@8d81000 { 919 compatible = "st,stih407-uni-player-pcm-out"; 920 #sound-dai-cells = <0>; 921 st,syscfg = <&syscfg_core>; 922 clocks = <&clk_s_d0_flexgen CLK_PCM_1>; 923 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; 924 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; 925 assigned-clock-rates = <50000000>; 926 reg = <0x8d81000 0x158>; 927 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 928 dmas = <&fdma0 3 0 1>; 929 dma-names = "tx"; 930 931 status = "disabled"; 932 }; 933 934 sti_uni_player2: sti-uni-player@8d82000 { 935 compatible = "st,stih407-uni-player-dac"; 936 #sound-dai-cells = <0>; 937 st,syscfg = <&syscfg_core>; 938 clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 939 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; 940 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; 941 assigned-clock-rates = <50000000>; 942 reg = <0x8d82000 0x158>; 943 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 944 dmas = <&fdma0 4 0 1>; 945 dma-names = "tx"; 946 947 status = "disabled"; 948 }; 949 950 sti_uni_player3: sti-uni-player@8d85000 { 951 compatible = "st,stih407-uni-player-spdif"; 952 #sound-dai-cells = <0>; 953 st,syscfg = <&syscfg_core>; 954 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; 955 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; 956 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; 957 assigned-clock-rates = <50000000>; 958 reg = <0x8d85000 0x158>; 959 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 960 dmas = <&fdma0 7 0 1>; 961 dma-names = "tx"; 962 963 status = "disabled"; 964 }; 965 966 sti_uni_reader0: sti-uni-reader@8d83000 { 967 compatible = "st,stih407-uni-reader-pcm_in"; 968 #sound-dai-cells = <0>; 969 st,syscfg = <&syscfg_core>; 970 reg = <0x8d83000 0x158>; 971 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 972 dmas = <&fdma0 5 0 1>; 973 dma-names = "rx"; 974 975 status = "disabled"; 976 }; 977 978 sti_uni_reader1: sti-uni-reader@8d84000 { 979 compatible = "st,stih407-uni-reader-hdmi"; 980 #sound-dai-cells = <0>; 981 st,syscfg = <&syscfg_core>; 982 reg = <0x8d84000 0x158>; 983 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 984 dmas = <&fdma0 6 0 1>; 985 dma-names = "rx"; 986 987 status = "disabled"; 988 }; 989 990 delta0@0 { 991 compatible = "st,st-delta"; 992 reg = <0 0>; 993 clock-names = "delta", 994 "delta-st231", 995 "delta-flash-promip"; 996 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, 997 <&clk_s_c0_flexgen CLK_ST231_DMU>, 998 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 999 }; 1000 }; 1001}; 1002