1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 STMicroelectronics R&D Limited
4 */
5#include <dt-bindings/clock/stih418-clks.h>
6/ {
7	/*
8	 * Fixed 30MHz oscillator inputs to SoC
9	 */
10	clk_sysin: clk-sysin {
11		#clock-cells = <0>;
12		compatible = "fixed-clock";
13		clock-frequency = <30000000>;
14		clock-output-names = "CLK_SYSIN";
15	};
16
17	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18		#clock-cells = <0>;
19		compatible = "fixed-clock";
20		clock-frequency = <0>;
21	};
22
23	clocks {
24		#address-cells = <1>;
25		#size-cells = <1>;
26		ranges;
27
28		compatible = "st,stih418-clk", "simple-bus";
29
30		/*
31		 * A9 PLL.
32		 */
33		clockgen-a9@92b0000 {
34			compatible = "st,clkgen-c32";
35			reg = <0x92b0000 0xffff>;
36
37			clockgen_a9_pll: clockgen-a9-pll {
38				#clock-cells = <1>;
39				compatible = "st,stih418-clkgen-plla9";
40
41				clocks = <&clk_sysin>;
42			};
43		};
44
45		/*
46		 * ARM CPU related clocks.
47		 */
48		clk_m_a9: clk-m-a9@92b0000 {
49			#clock-cells = <0>;
50			compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
51			reg = <0x92b0000 0x10000>;
52
53			clocks = <&clockgen_a9_pll 0>,
54				 <&clockgen_a9_pll 0>,
55				 <&clk_s_c0_flexgen 13>,
56				 <&clk_m_a9_ext2f_div2>;
57
58			/*
59			 * ARM Peripheral clock for timers
60			 */
61			arm_periph_clk: clk-m-a9-periphs {
62				#clock-cells = <0>;
63				compatible = "fixed-factor-clock";
64				clocks = <&clk_m_a9>;
65				clock-div = <2>;
66				clock-mult = <1>;
67			};
68		};
69
70		clockgen-a@90ff000 {
71			compatible = "st,clkgen-c32";
72			reg = <0x90ff000 0x1000>;
73
74			clk_s_a0_pll: clk-s-a0-pll {
75				#clock-cells = <1>;
76				compatible = "st,clkgen-pll0-a0";
77
78				clocks = <&clk_sysin>;
79			};
80
81			clk_s_a0_flexgen: clk-s-a0-flexgen {
82				compatible = "st,flexgen", "st,flexgen-stih410-a0";
83
84				#clock-cells = <1>;
85
86				clocks = <&clk_s_a0_pll 0>,
87					 <&clk_sysin>;
88			};
89		};
90
91		clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
92			#clock-cells = <1>;
93			compatible = "st,quadfs-pll";
94			reg = <0x9103000 0x1000>;
95
96			clocks = <&clk_sysin>;
97		};
98
99		clk_s_c0: clockgen-c@9103000 {
100			compatible = "st,clkgen-c32";
101			reg = <0x9103000 0x1000>;
102
103			clk_s_c0_pll0: clk-s-c0-pll0 {
104				#clock-cells = <1>;
105				compatible = "st,clkgen-pll0-c0";
106
107				clocks = <&clk_sysin>;
108			};
109
110			clk_s_c0_pll1: clk-s-c0-pll1 {
111				#clock-cells = <1>;
112				compatible = "st,clkgen-pll1-c0";
113
114				clocks = <&clk_sysin>;
115			};
116
117			clk_s_c0_flexgen: clk-s-c0-flexgen {
118				#clock-cells = <1>;
119				compatible = "st,flexgen", "st,flexgen-stih418-c0";
120
121				clocks = <&clk_s_c0_pll0 0>,
122					 <&clk_s_c0_pll1 0>,
123					 <&clk_s_c0_quadfs 0>,
124					 <&clk_s_c0_quadfs 1>,
125					 <&clk_s_c0_quadfs 2>,
126					 <&clk_s_c0_quadfs 3>,
127					 <&clk_sysin>;
128
129				/*
130				 * ARM Peripheral clock for timers
131				 */
132				clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
133					#clock-cells = <0>;
134					compatible = "fixed-factor-clock";
135
136					clocks = <&clk_s_c0_flexgen 13>;
137
138					clock-output-names = "clk-m-a9-ext2f-div2";
139
140					clock-div = <2>;
141					clock-mult = <1>;
142				};
143			};
144		};
145
146		clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
147			#clock-cells = <1>;
148			compatible = "st,quadfs-d0";
149			reg = <0x9104000 0x1000>;
150
151			clocks = <&clk_sysin>;
152		};
153
154		clockgen-d0@9104000 {
155			compatible = "st,clkgen-c32";
156			reg = <0x9104000 0x1000>;
157
158			clk_s_d0_flexgen: clk-s-d0-flexgen {
159				#clock-cells = <1>;
160				compatible = "st,flexgen", "st,flexgen-stih410-d0";
161
162				clocks = <&clk_s_d0_quadfs 0>,
163					 <&clk_s_d0_quadfs 1>,
164					 <&clk_s_d0_quadfs 2>,
165					 <&clk_s_d0_quadfs 3>,
166					 <&clk_sysin>;
167			};
168		};
169
170		clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
171			#clock-cells = <1>;
172			compatible = "st,quadfs-d2";
173			reg = <0x9106000 0x1000>;
174
175			clocks = <&clk_sysin>;
176		};
177
178		clockgen-d2@9106000 {
179			compatible = "st,clkgen-c32";
180			reg = <0x9106000 0x1000>;
181
182			clk_s_d2_flexgen: clk-s-d2-flexgen {
183				#clock-cells = <1>;
184				compatible = "st,flexgen", "st,flexgen-stih418-d2";
185
186				clocks = <&clk_s_d2_quadfs 0>,
187					 <&clk_s_d2_quadfs 1>,
188					 <&clk_s_d2_quadfs 2>,
189					 <&clk_s_d2_quadfs 3>,
190					 <&clk_sysin>,
191					 <&clk_sysin>,
192					 <&clk_tmdsout_hdmi>;
193			};
194		};
195
196		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
197			#clock-cells = <1>;
198			compatible = "st,quadfs-d3";
199			reg = <0x9107000 0x1000>;
200
201			clocks = <&clk_sysin>;
202		};
203
204		clockgen-d3@9107000 {
205			compatible = "st,clkgen-c32";
206			reg = <0x9107000 0x1000>;
207
208			clk_s_d3_flexgen: clk-s-d3-flexgen {
209				#clock-cells = <1>;
210				compatible = "st,flexgen", "st,flexgen-stih407-d3";
211
212				clocks = <&clk_s_d3_quadfs 0>,
213					 <&clk_s_d3_quadfs 1>,
214					 <&clk_s_d3_quadfs 2>,
215					 <&clk_s_d3_quadfs 3>,
216					 <&clk_sysin>;
217			};
218		};
219	};
220};
221