1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6/dts-v1/;
7
8#include "stm32mp157.dtsi"
9#include "stm32mp15xc.dtsi"
10#include "stm32mp15-pinctrl.dtsi"
11#include "stm32mp15xxaa-pinctrl.dtsi"
12#include <dt-bindings/clock/stm32mp1-clksrc.h>
13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
14
15/ {
16	model = "STMicroelectronics STM32MP157C eval daughter";
17	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	memory@c0000000 {
24		device_type = "memory";
25		reg = <0xC0000000 0x40000000>;
26	};
27
28	aliases {
29		serial0 = &uart4;
30	};
31};
32
33&bsec {
34	board_id: board_id@ec {
35		reg = <0xec 0x4>;
36		status = "okay";
37		secure-status = "okay";
38	};
39};
40
41&clk_hse {
42	st,digbypass;
43};
44
45&cpu0 {
46	cpu-supply = <&vddcore>;
47};
48
49&cpu1 {
50	cpu-supply = <&vddcore>;
51};
52
53&cryp1 {
54	status = "okay";
55};
56
57&hash1 {
58	status = "okay";
59};
60
61&i2c4 {
62	pinctrl-names = "default";
63	pinctrl-0 = <&i2c4_pins_a>;
64	i2c-scl-rising-time-ns = <185>;
65	i2c-scl-falling-time-ns = <20>;
66	clock-frequency = <400000>;
67	status = "okay";
68
69	pmic: stpmic@33 {
70		compatible = "st,stpmic1";
71		reg = <0x33>;
72		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
73		interrupt-controller;
74		#interrupt-cells = <2>;
75		status = "okay";
76
77		regulators {
78			compatible = "st,stpmic1-regulators";
79			ldo1-supply = <&v3v3>;
80			ldo2-supply = <&v3v3>;
81			ldo3-supply = <&vdd_ddr>;
82			ldo5-supply = <&v3v3>;
83			ldo6-supply = <&v3v3>;
84			pwr_sw1-supply = <&bst_out>;
85			pwr_sw2-supply = <&bst_out>;
86
87			vddcore: buck1 {
88				regulator-name = "vddcore";
89				regulator-min-microvolt = <1200000>;
90				regulator-max-microvolt = <1350000>;
91				regulator-always-on;
92				regulator-initial-mode = <0>;
93				regulator-over-current-protection;
94			};
95
96			vdd_ddr: buck2 {
97				regulator-name = "vdd_ddr";
98				regulator-min-microvolt = <1350000>;
99				regulator-max-microvolt = <1350000>;
100				regulator-always-on;
101				regulator-initial-mode = <0>;
102				regulator-over-current-protection;
103			};
104
105			vdd: buck3 {
106				regulator-name = "vdd";
107				regulator-min-microvolt = <3300000>;
108				regulator-max-microvolt = <3300000>;
109				regulator-always-on;
110				st,mask-reset;
111				regulator-initial-mode = <0>;
112				regulator-over-current-protection;
113			};
114
115			v3v3: buck4 {
116				regulator-name = "v3v3";
117				regulator-min-microvolt = <3300000>;
118				regulator-max-microvolt = <3300000>;
119				regulator-always-on;
120				regulator-over-current-protection;
121				regulator-initial-mode = <0>;
122			};
123
124			vdda: ldo1 {
125				regulator-name = "vdda";
126				regulator-min-microvolt = <2900000>;
127				regulator-max-microvolt = <2900000>;
128			};
129
130			v2v8: ldo2 {
131				regulator-name = "v2v8";
132				regulator-min-microvolt = <2800000>;
133				regulator-max-microvolt = <2800000>;
134			};
135
136			vtt_ddr: ldo3 {
137				regulator-name = "vtt_ddr";
138				regulator-min-microvolt = <500000>;
139				regulator-max-microvolt = <750000>;
140				regulator-always-on;
141				regulator-over-current-protection;
142			};
143
144			vdd_usb: ldo4 {
145				regulator-name = "vdd_usb";
146			};
147
148			vdd_sd: ldo5 {
149				regulator-name = "vdd_sd";
150				regulator-min-microvolt = <2900000>;
151				regulator-max-microvolt = <2900000>;
152				regulator-boot-on;
153			};
154
155			v1v8: ldo6 {
156				regulator-name = "v1v8";
157				regulator-min-microvolt = <1800000>;
158				regulator-max-microvolt = <1800000>;
159			};
160
161			vref_ddr: vref_ddr {
162				regulator-name = "vref_ddr";
163				regulator-always-on;
164			};
165
166			bst_out: boost {
167				regulator-name = "bst_out";
168			};
169
170			vbus_otg: pwr_sw1 {
171				regulator-name = "vbus_otg";
172			 };
173
174			 vbus_sw: pwr_sw2 {
175				regulator-name = "vbus_sw";
176				regulator-active-discharge = <1>;
177			 };
178		};
179
180		onkey {
181			compatible = "st,stpmic1-onkey";
182			power-off-time-sec = <10>;
183			status = "okay";
184		};
185
186		watchdog {
187			compatible = "st,stpmic1-wdt";
188			status = "disabled";
189		};
190	};
191};
192
193&iwdg2 {
194	timeout-sec = <32>;
195	status = "okay";
196};
197
198&pwr_regulators {
199	vdd-supply = <&vdd>;
200	vdd_3v3_usbfs-supply = <&vdd_usb>;
201};
202
203&rcc {
204	secure-status = "disabled";
205	st,clksrc = <
206		CLK_MPU_PLL1P
207		CLK_AXI_PLL2P
208		CLK_MCU_PLL3P
209		CLK_PLL12_HSE
210		CLK_PLL3_HSE
211		CLK_PLL4_HSE
212		CLK_RTC_LSE
213		CLK_MCO1_DISABLED
214		CLK_MCO2_DISABLED
215	>;
216
217	st,clkdiv = <
218		1 /*MPU*/
219		0 /*AXI*/
220		0 /*MCU*/
221		1 /*APB1*/
222		1 /*APB2*/
223		1 /*APB3*/
224		1 /*APB4*/
225		2 /*APB5*/
226		23 /*RTC*/
227		0 /*MCO1*/
228		0 /*MCO2*/
229	>;
230
231	st,pkcs = <
232		CLK_CKPER_HSE
233		CLK_FMC_ACLK
234		CLK_QSPI_ACLK
235		CLK_ETH_PLL4P
236		CLK_SDMMC12_PLL4P
237		CLK_DSI_DSIPLL
238		CLK_STGEN_HSE
239		CLK_USBPHY_HSE
240		CLK_SPI2S1_PLL3Q
241		CLK_SPI2S23_PLL3Q
242		CLK_SPI45_HSI
243		CLK_SPI6_HSI
244		CLK_I2C46_HSI
245		CLK_SDMMC3_PLL4P
246		CLK_USBO_USBPHY
247		CLK_ADC_CKPER
248		CLK_CEC_LSE
249		CLK_I2C12_HSI
250		CLK_I2C35_HSI
251		CLK_UART1_HSI
252		CLK_UART24_HSI
253		CLK_UART35_HSI
254		CLK_UART6_HSI
255		CLK_UART78_HSI
256		CLK_SPDIF_PLL4P
257		CLK_FDCAN_PLL4R
258		CLK_SAI1_PLL3Q
259		CLK_SAI2_PLL3Q
260		CLK_SAI3_PLL3Q
261		CLK_SAI4_PLL3Q
262		CLK_RNG1_LSI
263		CLK_RNG2_LSI
264		CLK_LPTIM1_PCLK1
265		CLK_LPTIM23_PCLK3
266		CLK_LPTIM45_LSE
267	>;
268
269	/* VCO = 1300.0 MHz => P = 650 (CPU) */
270	pll1: st,pll@0 {
271		compatible = "st,stm32mp1-pll";
272		reg = <0>;
273		cfg = <2 80 0 0 0 PQR(1,0,0)>;
274		frac = <0x800>;
275	};
276
277	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
278	pll2: st,pll@1 {
279		compatible = "st,stm32mp1-pll";
280		reg = <1>;
281		cfg = <2 65 1 0 0 PQR(1,1,1)>;
282		frac = <0x1400>;
283	};
284
285	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
286	pll3: st,pll@2 {
287		compatible = "st,stm32mp1-pll";
288		reg = <2>;
289		cfg = <1 33 1 16 36 PQR(1,1,1)>;
290		frac = <0x1a04>;
291	};
292
293	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
294	pll4: st,pll@3 {
295		compatible = "st,stm32mp1-pll";
296		reg = <3>;
297		cfg = <3 98 5 7 7 PQR(1,1,1)>;
298	};
299};
300
301&rng1 {
302	status = "okay";
303};
304
305&rtc {
306	status = "okay";
307};
308
309&sdmmc1 {
310	pinctrl-names = "default";
311	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
312	disable-wp;
313	st,sig-dir;
314	st,neg-edge;
315	st,use-ckin;
316	bus-width = <4>;
317	vmmc-supply = <&vdd_sd>;
318	sd-uhs-sdr12;
319	sd-uhs-sdr25;
320	sd-uhs-sdr50;
321	sd-uhs-ddr50;
322	status = "okay";
323};
324
325&sdmmc2 {
326	pinctrl-names = "default";
327	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
328	non-removable;
329	no-sd;
330	no-sdio;
331	st,neg-edge;
332	bus-width = <8>;
333	vmmc-supply = <&v3v3>;
334	vqmmc-supply = <&vdd>;
335	mmc-ddr-3_3v;
336	status = "okay";
337};
338
339&uart4 {
340	pinctrl-names = "default";
341	pinctrl-0 = <&uart4_pins_a>;
342	status = "okay";
343};
344