1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Apple T8103 "M1" SoC
4 *
5 * Other names: H13G, "Tonga"
6 *
7 * Copyright The Asahi Linux Contributors
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/apple-aic.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/pinctrl/apple.h>
14
15/ {
16	compatible = "apple,t8103", "apple,arm-platform";
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	cpus {
22		#address-cells = <2>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			compatible = "apple,icestorm";
27			device_type = "cpu";
28			reg = <0x0 0x0>;
29			enable-method = "spin-table";
30			cpu-release-addr = <0 0>; /* To be filled by loader */
31		};
32
33		cpu1: cpu@1 {
34			compatible = "apple,icestorm";
35			device_type = "cpu";
36			reg = <0x0 0x1>;
37			enable-method = "spin-table";
38			cpu-release-addr = <0 0>; /* To be filled by loader */
39		};
40
41		cpu2: cpu@2 {
42			compatible = "apple,icestorm";
43			device_type = "cpu";
44			reg = <0x0 0x2>;
45			enable-method = "spin-table";
46			cpu-release-addr = <0 0>; /* To be filled by loader */
47		};
48
49		cpu3: cpu@3 {
50			compatible = "apple,icestorm";
51			device_type = "cpu";
52			reg = <0x0 0x3>;
53			enable-method = "spin-table";
54			cpu-release-addr = <0 0>; /* To be filled by loader */
55		};
56
57		cpu4: cpu@10100 {
58			compatible = "apple,firestorm";
59			device_type = "cpu";
60			reg = <0x0 0x10100>;
61			enable-method = "spin-table";
62			cpu-release-addr = <0 0>; /* To be filled by loader */
63		};
64
65		cpu5: cpu@10101 {
66			compatible = "apple,firestorm";
67			device_type = "cpu";
68			reg = <0x0 0x10101>;
69			enable-method = "spin-table";
70			cpu-release-addr = <0 0>; /* To be filled by loader */
71		};
72
73		cpu6: cpu@10102 {
74			compatible = "apple,firestorm";
75			device_type = "cpu";
76			reg = <0x0 0x10102>;
77			enable-method = "spin-table";
78			cpu-release-addr = <0 0>; /* To be filled by loader */
79		};
80
81		cpu7: cpu@10103 {
82			compatible = "apple,firestorm";
83			device_type = "cpu";
84			reg = <0x0 0x10103>;
85			enable-method = "spin-table";
86			cpu-release-addr = <0 0>; /* To be filled by loader */
87		};
88	};
89
90	timer {
91		compatible = "arm,armv8-timer";
92		interrupt-parent = <&aic>;
93		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
94		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
95			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
96			     <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
97			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
98	};
99
100	clk24: clock-24m {
101		compatible = "fixed-clock";
102		#clock-cells = <0>;
103		clock-frequency = <24000000>;
104		clock-output-names = "clk24";
105	};
106
107	soc {
108		compatible = "simple-bus";
109		#address-cells = <2>;
110		#size-cells = <2>;
111
112		ranges;
113		nonposted-mmio;
114
115		serial0: serial@235200000 {
116			compatible = "apple,s5l-uart";
117			reg = <0x2 0x35200000 0x0 0x1000>;
118			reg-io-width = <4>;
119			interrupt-parent = <&aic>;
120			interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
121			/*
122			 * TODO: figure out the clocking properly, there may
123			 * be a third selectable clock.
124			 */
125			clocks = <&clk24>, <&clk24>;
126			clock-names = "uart", "clk_uart_baud0";
127			status = "disabled";
128		};
129
130		aic: interrupt-controller@23b100000 {
131			compatible = "apple,t8103-aic", "apple,aic";
132			#interrupt-cells = <3>;
133			interrupt-controller;
134			reg = <0x2 0x3b100000 0x0 0x8000>;
135		};
136
137		pinctrl_ap: pinctrl@23c100000 {
138			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
139			reg = <0x2 0x3c100000 0x0 0x100000>;
140
141			gpio-controller;
142			#gpio-cells = <2>;
143			gpio-ranges = <&pinctrl_ap 0 0 212>;
144			apple,npins = <212>;
145
146			interrupt-controller;
147			#interrupt-cells = <2>;
148			interrupt-parent = <&aic>;
149			interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
150				     <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
151				     <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
152				     <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
153				     <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
154				     <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
155				     <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
156
157			pcie_pins: pcie-pins {
158				pinmux = <APPLE_PINMUX(150, 1)>,
159					 <APPLE_PINMUX(151, 1)>,
160					 <APPLE_PINMUX(32, 1)>;
161			};
162		};
163
164		pinctrl_aop: pinctrl@24a820000 {
165			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
166			reg = <0x2 0x4a820000 0x0 0x4000>;
167
168			gpio-controller;
169			#gpio-cells = <2>;
170			gpio-ranges = <&pinctrl_aop 0 0 42>;
171			apple,npins = <42>;
172
173			interrupt-controller;
174			#interrupt-cells = <2>;
175			interrupt-parent = <&aic>;
176			interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
177				     <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
178				     <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
179				     <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
180				     <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
181				     <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
182				     <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
183		};
184
185		pinctrl_nub: pinctrl@23d1f0000 {
186			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
187			reg = <0x2 0x3d1f0000 0x0 0x4000>;
188
189			gpio-controller;
190			#gpio-cells = <2>;
191			gpio-ranges = <&pinctrl_nub 0 0 23>;
192			apple,npins = <23>;
193
194			interrupt-controller;
195			#interrupt-cells = <2>;
196			interrupt-parent = <&aic>;
197			interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
198				     <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
199				     <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
200				     <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
201				     <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
202				     <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
203				     <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
204		};
205
206		pinctrl_smc: pinctrl@23e820000 {
207			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
208			reg = <0x2 0x3e820000 0x0 0x4000>;
209
210			gpio-controller;
211			#gpio-cells = <2>;
212			gpio-ranges = <&pinctrl_smc 0 0 16>;
213			apple,npins = <16>;
214
215			interrupt-controller;
216			#interrupt-cells = <2>;
217			interrupt-parent = <&aic>;
218			interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
219				     <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
220				     <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
221				     <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
222				     <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
223				     <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
224				     <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
225		};
226
227		pcie0_dart_0: dart@681008000 {
228			compatible = "apple,t8103-dart";
229			reg = <0x6 0x81008000 0x0 0x4000>;
230			#iommu-cells = <1>;
231			interrupt-parent = <&aic>;
232			interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
233		};
234
235		pcie0_dart_1: dart@682008000 {
236			compatible = "apple,t8103-dart";
237			reg = <0x6 0x82008000 0x0 0x4000>;
238			#iommu-cells = <1>;
239			interrupt-parent = <&aic>;
240			interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
241		};
242
243		pcie0_dart_2: dart@683008000 {
244			compatible = "apple,t8103-dart";
245			reg = <0x6 0x83008000 0x0 0x4000>;
246			#iommu-cells = <1>;
247			interrupt-parent = <&aic>;
248			interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
249		};
250
251		pcie0: pcie@690000000 {
252			compatible = "apple,t8103-pcie", "apple,pcie";
253			device_type = "pci";
254
255			reg = <0x6 0x90000000 0x0 0x1000000>,
256			      <0x6 0x80000000 0x0 0x100000>,
257			      <0x6 0x81000000 0x0 0x4000>,
258			      <0x6 0x82000000 0x0 0x4000>,
259			      <0x6 0x83000000 0x0 0x4000>;
260			reg-names = "config", "rc", "port0", "port1", "port2";
261
262			interrupt-parent = <&aic>;
263			interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
264				     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
265				     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
266
267			msi-controller;
268			msi-parent = <&pcie0>;
269			msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
270
271
272			iommu-map = <0x100 &pcie0_dart_0 1 1>,
273				    <0x200 &pcie0_dart_1 1 1>,
274				    <0x300 &pcie0_dart_2 1 1>;
275			iommu-map-mask = <0xff00>;
276
277			bus-range = <0 3>;
278			#address-cells = <3>;
279			#size-cells = <2>;
280			ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
281				 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
282
283			pinctrl-0 = <&pcie_pins>;
284			pinctrl-names = "default";
285
286			port00: pci@0,0 {
287				device_type = "pci";
288				reg = <0x0 0x0 0x0 0x0 0x0>;
289				reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
290				max-link-speed = <2>;
291
292				#address-cells = <3>;
293				#size-cells = <2>;
294				ranges;
295
296				interrupt-controller;
297				#interrupt-cells = <1>;
298
299				interrupt-map-mask = <0 0 0 7>;
300				interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
301						<0 0 0 2 &port00 0 0 0 1>,
302						<0 0 0 3 &port00 0 0 0 2>,
303						<0 0 0 4 &port00 0 0 0 3>;
304			};
305
306			port01: pci@1,0 {
307				device_type = "pci";
308				reg = <0x800 0x0 0x0 0x0 0x0>;
309				reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
310				max-link-speed = <2>;
311
312				#address-cells = <3>;
313				#size-cells = <2>;
314				ranges;
315
316				interrupt-controller;
317				#interrupt-cells = <1>;
318
319				interrupt-map-mask = <0 0 0 7>;
320				interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
321						<0 0 0 2 &port01 0 0 0 1>,
322						<0 0 0 3 &port01 0 0 0 2>,
323						<0 0 0 4 &port01 0 0 0 3>;
324			};
325
326			port02: pci@2,0 {
327				device_type = "pci";
328				reg = <0x1000 0x0 0x0 0x0 0x0>;
329				reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
330				max-link-speed = <1>;
331
332				#address-cells = <3>;
333				#size-cells = <2>;
334				ranges;
335
336				interrupt-controller;
337				#interrupt-cells = <1>;
338
339				interrupt-map-mask = <0 0 0 7>;
340				interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
341						<0 0 0 2 &port02 0 0 0 1>,
342						<0 0 0 3 &port02 0 0 0 2>,
343						<0 0 0 4 &port02 0 0 0 3>;
344			};
345		};
346	};
347};
348