1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2019 Google LLC 4 * 5 * Taken from coreboot file of the same name 6 */ 7 8 #ifndef BASEBOARD_GPIO_H 9 #define BASEBOARD_GPIO_H 10 11 #include <asm/arch/gpio.h> 12 #include <ec_commands.h> 13 14 /* 15 * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 16 * which is North community 17 */ 18 #define EC_SCI_GPI GPE0_DW1_11 19 20 /* EC SMI */ 21 #define EC_SMI_GPI GPIO_49 22 23 /* 24 * On lidopen/lidclose GPIO_22 from North Community gets toggled and 25 * is used in _PRW to wake up device from sleep. GPIO_22 maps to 26 * group GPIO_GPE_N_31_0 and the pad is configured as SCI with 27 * EDGE_SINGLE and INVERT. 28 */ 29 #define GPE_EC_WAKE GPE0_DW1_22 30 31 /* Write Protect and indication if EC is in RW code. */ 32 #define GPIO_PCH_WP GPIO_75 33 #define GPIO_EC_IN_RW GPIO_41 34 /* Determine if board is in final shipping mode. */ 35 #define GPIO_SHIP_MODE GPIO_10 36 37 /* Memory SKU GPIOs. */ 38 #define MEM_CONFIG3 GPIO_45 39 #define MEM_CONFIG2 GPIO_38 40 #define MEM_CONFIG1 GPIO_102 41 #define MEM_CONFIG0 GPIO_101 42 43 /* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */ 44 #define DMIC_CONFIG_PIN GPIO_17 45 46 #ifndef __ASSEMBLY__ 47 48 enum cros_gpio_t { 49 CROS_GPIO_REC = 1, /* Recovery */ 50 51 /* Developer; * deprecated (chromium:942901) */ 52 CROS_GPIO_DEPRECATED_DEV = 2, 53 CROS_GPIO_WP = 3, /* Write Protect */ 54 CROS_GPIO_PE = 4, /* Phase enforcement for final product */ 55 56 CROS_GPIO_ACTIVE_LOW = 0, 57 CROS_GPIO_ACTIVE_HIGH = 1, 58 59 CROS_GPIO_VIRTUAL = -1, 60 }; 61 #endif 62 63 #endif /* BASEBOARD_GPIO_H */ 64