1 /*
2 * xen/drivers/char/scif-uart.c
3 *
4 * Driver for SCIF(A) (Serial communication interface with FIFO (A))
5 * compatible UART.
6 *
7 * Oleksandr Tyshchenko <oleksandr.tyshchenko@globallogic.com>
8 * Copyright (C) 2014, Globallogic.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <xen/console.h>
22 #include <xen/errno.h>
23 #include <xen/serial.h>
24 #include <xen/init.h>
25 #include <xen/irq.h>
26 #include <xen/mm.h>
27 #include <xen/delay.h>
28 #include <asm/device.h>
29 #include <asm/scif-uart.h>
30 #include <asm/io.h>
31
32 #define scif_readb(uart, off) readb((uart)->regs + (off))
33 #define scif_writeb(uart, off, val) writeb((val), (uart)->regs + (off))
34
35 #define scif_readw(uart, off) readw((uart)->regs + (off))
36 #define scif_writew(uart, off, val) writew((val), (uart)->regs + (off))
37
38 static struct scif_uart {
39 unsigned int irq;
40 char __iomem *regs;
41 struct irqaction irqaction;
42 struct vuart_info vuart;
43 const struct port_params *params;
44 } scif_com = {0};
45
46 enum port_types
47 {
48 SCIF_PORT,
49 SCIFA_PORT,
50 NR_PORTS,
51 };
52
53 struct port_params
54 {
55 unsigned int status_reg;
56 unsigned int tx_fifo_reg;
57 unsigned int rx_fifo_reg;
58 unsigned int overrun_reg;
59 unsigned int overrun_mask;
60 unsigned int error_mask;
61 unsigned int irq_flags;
62 unsigned int fifo_size;
63 };
64
65 static const struct port_params port_params[NR_PORTS] =
66 {
67 [SCIF_PORT] =
68 {
69 .status_reg = SCIF_SCFSR,
70 .tx_fifo_reg = SCIF_SCFTDR,
71 .rx_fifo_reg = SCIF_SCFRDR,
72 .overrun_reg = SCIF_SCLSR,
73 .overrun_mask = SCLSR_ORER,
74 .error_mask = SCFSR_PER | SCFSR_FER | SCFSR_BRK | SCFSR_ER,
75 .irq_flags = SCSCR_RIE | SCSCR_TIE | SCSCR_REIE,
76 .fifo_size = 16,
77 },
78
79 [SCIFA_PORT] =
80 {
81 .status_reg = SCIFA_SCASSR,
82 .tx_fifo_reg = SCIFA_SCAFTDR,
83 .rx_fifo_reg = SCIFA_SCAFRDR,
84 .overrun_reg = SCIFA_SCASSR,
85 .overrun_mask = SCASSR_ORER,
86 .error_mask = SCASSR_PER | SCASSR_FER | SCASSR_BRK | SCASSR_ER,
87 .irq_flags = SCASCR_RIE | SCASCR_TIE | SCASCR_DRIE | SCASCR_ERIE |
88 SCASCR_BRIE,
89 .fifo_size = 64,
90 },
91 };
92
scif_uart_interrupt(int irq,void * data,struct cpu_user_regs * regs)93 static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs)
94 {
95 struct serial_port *port = data;
96 struct scif_uart *uart = port->uart;
97 const struct port_params *params = uart->params;
98 uint16_t status, ctrl;
99
100 ctrl = scif_readw(uart, SCIF_SCSCR);
101 status = scif_readw(uart, params->status_reg) & ~SCFSR_TEND;
102 /* Ignore next flag if TX Interrupt is disabled */
103 if ( !(ctrl & SCSCR_TIE) )
104 status &= ~SCFSR_TDFE;
105
106 while ( status != 0 )
107 {
108 /* TX Interrupt */
109 if ( status & SCFSR_TDFE )
110 serial_tx_interrupt(port, regs);
111
112 /* RX Interrupt */
113 if ( status & (SCFSR_RDF | SCFSR_DR) )
114 serial_rx_interrupt(port, regs);
115
116 /* Error Interrupt */
117 if ( status & params->error_mask )
118 scif_writew(uart, params->status_reg, ~params->error_mask);
119 if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask )
120 scif_writew(uart, params->overrun_reg, ~params->overrun_mask);
121
122 ctrl = scif_readw(uart, SCIF_SCSCR);
123 status = scif_readw(uart, params->status_reg) & ~SCFSR_TEND;
124 /* Ignore next flag if TX Interrupt is disabled */
125 if ( !(ctrl & SCSCR_TIE) )
126 status &= ~SCFSR_TDFE;
127 }
128 }
129
scif_uart_init_preirq(struct serial_port * port)130 static void __init scif_uart_init_preirq(struct serial_port *port)
131 {
132 struct scif_uart *uart = port->uart;
133 const struct port_params *params = uart->params;
134
135 /*
136 * Wait until last bit has been transmitted. This is needed for a smooth
137 * transition when we come from early printk
138 */
139 while ( !(scif_readw(uart, params->status_reg) & SCFSR_TEND) );
140
141 /* Disable TX/RX parts and all interrupts */
142 scif_writew(uart, SCIF_SCSCR, 0);
143
144 /* Reset TX/RX FIFOs */
145 scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST);
146
147 /* Clear all errors and flags */
148 scif_readw(uart, params->status_reg);
149 scif_writew(uart, params->status_reg, 0);
150 scif_readw(uart, params->overrun_reg);
151 scif_writew(uart, params->overrun_reg, 0);
152
153 /* Setup trigger level for TX/RX FIFOs */
154 scif_writew(uart, SCIF_SCFCR, SCFCR_RTRG11 | SCFCR_TTRG11);
155
156 /* Enable TX/RX parts */
157 scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) |
158 SCSCR_TE | SCSCR_RE);
159 }
160
scif_uart_init_postirq(struct serial_port * port)161 static void __init scif_uart_init_postirq(struct serial_port *port)
162 {
163 struct scif_uart *uart = port->uart;
164 const struct port_params *params = uart->params;
165 int rc;
166
167 uart->irqaction.handler = scif_uart_interrupt;
168 uart->irqaction.name = "scif_uart";
169 uart->irqaction.dev_id = port;
170
171 if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 )
172 dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n",
173 uart->irq);
174
175 /* Clear all errors */
176 if ( scif_readw(uart, params->status_reg) & params->error_mask )
177 scif_writew(uart, params->status_reg, ~params->error_mask);
178 if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask )
179 scif_writew(uart, params->overrun_reg, ~params->overrun_mask);
180
181 /* Enable TX/RX and Error Interrupts */
182 scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) |
183 params->irq_flags);
184 }
185
scif_uart_suspend(struct serial_port * port)186 static void scif_uart_suspend(struct serial_port *port)
187 {
188 BUG();
189 }
190
scif_uart_resume(struct serial_port * port)191 static void scif_uart_resume(struct serial_port *port)
192 {
193 BUG();
194 }
195
scif_uart_tx_ready(struct serial_port * port)196 static int scif_uart_tx_ready(struct serial_port *port)
197 {
198 struct scif_uart *uart = port->uart;
199 const struct port_params *params = uart->params;
200 uint16_t cnt;
201
202 /* Check for empty space in TX FIFO */
203 if ( !(scif_readw(uart, params->status_reg) & SCFSR_TDFE) )
204 return 0;
205
206 /* Check number of data bytes stored in TX FIFO */
207 cnt = scif_readw(uart, SCIF_SCFDR) >> 8;
208 ASSERT( cnt <= params->fifo_size );
209
210 return (params->fifo_size - cnt);
211 }
212
scif_uart_putc(struct serial_port * port,char c)213 static void scif_uart_putc(struct serial_port *port, char c)
214 {
215 struct scif_uart *uart = port->uart;
216 const struct port_params *params = uart->params;
217
218 scif_writeb(uart, params->tx_fifo_reg, c);
219 /* Clear required TX flags */
220 scif_writew(uart, params->status_reg,
221 scif_readw(uart, params->status_reg) &
222 ~(SCFSR_TEND | SCFSR_TDFE));
223 }
224
scif_uart_getc(struct serial_port * port,char * pc)225 static int scif_uart_getc(struct serial_port *port, char *pc)
226 {
227 struct scif_uart *uart = port->uart;
228 const struct port_params *params = uart->params;
229
230 /* Check for available data bytes in RX FIFO */
231 if ( !(scif_readw(uart, params->status_reg) & (SCFSR_RDF | SCFSR_DR)) )
232 return 0;
233
234 *pc = scif_readb(uart, params->rx_fifo_reg);
235
236 /* dummy read */
237 scif_readw(uart, params->status_reg);
238 /* Clear required RX flags */
239 scif_writew(uart, params->status_reg, ~(SCFSR_RDF | SCFSR_DR));
240
241 return 1;
242 }
243
scif_uart_irq(struct serial_port * port)244 static int __init scif_uart_irq(struct serial_port *port)
245 {
246 struct scif_uart *uart = port->uart;
247
248 return ((uart->irq > 0) ? uart->irq : -1);
249 }
250
scif_vuart_info(struct serial_port * port)251 static const struct vuart_info *scif_vuart_info(struct serial_port *port)
252 {
253 struct scif_uart *uart = port->uart;
254
255 return &uart->vuart;
256 }
257
scif_uart_start_tx(struct serial_port * port)258 static void scif_uart_start_tx(struct serial_port *port)
259 {
260 struct scif_uart *uart = port->uart;
261
262 scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | SCSCR_TIE);
263 }
264
scif_uart_stop_tx(struct serial_port * port)265 static void scif_uart_stop_tx(struct serial_port *port)
266 {
267 struct scif_uart *uart = port->uart;
268
269 scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) & ~SCSCR_TIE);
270 }
271
272 static struct uart_driver __read_mostly scif_uart_driver = {
273 .init_preirq = scif_uart_init_preirq,
274 .init_postirq = scif_uart_init_postirq,
275 .endboot = NULL,
276 .suspend = scif_uart_suspend,
277 .resume = scif_uart_resume,
278 .tx_ready = scif_uart_tx_ready,
279 .putc = scif_uart_putc,
280 .getc = scif_uart_getc,
281 .irq = scif_uart_irq,
282 .start_tx = scif_uart_start_tx,
283 .stop_tx = scif_uart_stop_tx,
284 .vuart_info = scif_vuart_info,
285 };
286
287 static const struct dt_device_match scif_uart_dt_match[] __initconst =
288 {
289 { .compatible = "renesas,scif", .data = (void *)SCIF_PORT },
290 { .compatible = "renesas,scifa", .data = (void *)SCIFA_PORT },
291 { /* sentinel */ },
292 };
293
scif_uart_init(struct dt_device_node * dev,const void * data)294 static int __init scif_uart_init(struct dt_device_node *dev,
295 const void *data)
296 {
297 const struct dt_device_match *match;
298 const char *config = data;
299 struct scif_uart *uart;
300 int res;
301 u64 addr, size;
302
303 if ( strcmp(config, "") )
304 printk("WARNING: UART configuration is not supported\n");
305
306 uart = &scif_com;
307
308 res = dt_device_get_address(dev, 0, &addr, &size);
309 if ( res )
310 {
311 printk("scif-uart: Unable to retrieve the base"
312 " address of the UART\n");
313 return res;
314 }
315
316 res = platform_get_irq(dev, 0);
317 if ( res < 0 )
318 {
319 printk("scif-uart: Unable to retrieve the IRQ\n");
320 return res;
321 }
322 uart->irq = res;
323
324 uart->regs = ioremap_nocache(addr, size);
325 if ( !uart->regs )
326 {
327 printk("scif-uart: Unable to map the UART memory\n");
328 return -ENOMEM;
329 }
330
331 match = dt_match_node(scif_uart_dt_match, dev);
332 ASSERT( match );
333 uart->params = &port_params[(enum port_types)match->data];
334
335 uart->vuart.base_addr = addr;
336 uart->vuart.size = size;
337 uart->vuart.data_off = uart->params->tx_fifo_reg;
338 uart->vuart.status_off = uart->params->status_reg;
339 uart->vuart.status = SCFSR_TDFE;
340
341 /* Register with generic serial driver */
342 serial_register_uart(SERHND_DTUART, &scif_uart_driver, uart);
343
344 dt_device_set_used_by(dev, DOMID_XEN);
345
346 return 0;
347 }
348
349 DT_DEVICE_START(scif_uart, "SCIF UART", DEVICE_SERIAL)
350 .dt_match = scif_uart_dt_match,
351 .init = scif_uart_init,
352 DT_DEVICE_END
353
354 /*
355 * Local variables:
356 * mode: C
357 * c-file-style: "BSD"
358 * c-basic-offset: 4
359 * indent-tabs-mode: nil
360 * End:
361 */
362