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/linux/arch/arm/net/
A Dbpf_jit_32.h168 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
172 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
175 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
179 #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm) argument
189 #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) argument
217 #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm) argument
218 #define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm) argument
219 #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm) argument
236 #define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm) argument
248 #define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm)) argument
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A Dbpf_jit_32.c812 emit(ARM_LSL_I(rd, rd, val), ctx); in emit_a32_alu_i()
815 emit(ARM_LSR_I(rd, rd, val), ctx); in emit_a32_alu_i()
818 emit(ARM_ASR_I(rd, rd, val), ctx); in emit_a32_alu_i()
821 emit(ARM_RSB_I(rd, rd, val), ctx); in emit_a32_alu_i()
937 emit(ARM_EOR_R(rd[1], rd[1], rd[1]), ctx); in emit_a32_lsh_i64()
963 emit(ARM_MOV_R(rd[1], rd[0]), ctx); in emit_a32_rsh_i64()
1570 emit_rev16(rd[1], rd[1], ctx); in build_insn()
1573 emit_rev32(rd[1], rd[1], ctx); in build_insn()
1577 emit_rev32(rd[1], rd[0], ctx); in build_insn()
1593 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx); in build_insn()
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/linux/arch/riscv/net/
A Dbpf_jit.h229 (rd << 7) | opcode; in rv_r_insn()
826 if (rvc_enabled() && rd && rd == rs1 && rs2) in emit_add()
839 else if (rvc_enabled() && rd && rd == rs && imm && is_6b_int(imm)) in emit_addi()
855 if (rvc_enabled() && rd && rd != RV_REG_SP && is_6b_int(imm) && imm) in emit_lui()
871 if (rvc_enabled() && is_creg(rd) && rd == rs && is_6b_int(imm)) in emit_andi()
895 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_sub()
903 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_or()
911 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_and()
919 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) in emit_xor()
950 if (rvc_enabled() && rd && rd == rs && is_6b_int(imm)) in emit_addiw()
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A Dbpf_jit_comp64.c177 emit_slli(rd, rd, shift, ctx); in emit_imm()
554 emit_add(rd, rd, rs, ctx); in bpf_jit_emit_insn()
570 emit_and(rd, rd, rs, ctx); in bpf_jit_emit_insn()
576 emit_or(rd, rd, rs, ctx); in bpf_jit_emit_insn()
582 emit_xor(rd, rd, rs, ctx); in bpf_jit_emit_insn()
588 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
594 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
600 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
606 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
612 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
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A Dbpf_jit_comp32.c118 emit(rv_addi(rd, rd, lower), ctx); in emit_imm()
265 emit(rv_ori(lo(rd), lo(rd), imm), ctx); in emit_alu_i64()
281 emit(rv_xori(hi(rd), hi(rd), -1), ctx); in emit_alu_i64()
312 emit(rv_srai(hi(rd), hi(rd), 31), ctx); in emit_alu_i64()
422 emit(rv_slli(hi(rd), hi(rd), 1), ctx); in emit_alu_r64()
424 emit(rv_slli(lo(rd), lo(rd), 1), ctx); in emit_alu_r64()
919 emit(rv_slli(rd, rd, 16), ctx); in emit_rev16()
921 emit(rv_srli(rd, rd, 8), ctx); in emit_rev16()
932 emit(rv_srli(rd, rd, 8), ctx); in emit_rev32()
936 emit(rv_srli(rd, rd, 8), ctx); in emit_rev32()
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/linux/arch/arm/include/debug/
A Dsamsung.S14 ARM_BE8(rev \rd, \rd)
15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
20 ARM_BE8(rev \rd, \rd)
29 ARM_BE8(rev \rd, \rd)
30 and \rd, \rd, #S3C2440_UFSTAT_TXMASK
39 ARM_BE8(rev \rd, \rd)
53 ARM_BE8(rev \rd, \rd)
65 ARM_BE8(rev \rd, \rd)
77 ARM_BE8(rev \rd, \rd)
83 teq \rd, #0
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A D8250.S16 ARM_BE8(rev \rd, \rd)
17 str \rd, \rx
18 ARM_BE8(rev \rd, \rd)
22 ldr \rd, \rx
23 ARM_BE8(rev \rd, \rd)
27 strb \rd, \rx
31 ldrb \rd, \rx
37 .macro senduart,rd,rx
41 .macro busyuart,rd,rx
43 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
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A Dmsm.S15 ARM_BE8(rev \rd, \rd )
17 str \rd, [\rx, #0x70]
25 ldr \rd, [\rx, #0x08]
26 ARM_BE8(rev \rd, \rd )
27 tst \rd, #0x08
31 ARM_BE8(rev \rd, \rd )
32 tst \rd, #0x80
36 mov \rd, #0x300
37 ARM_BE8(rev \rd, \rd )
40 mov \rd, #0x1
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A Dicedcc.S15 .macro senduart, rd, rx
16 mcr p14, 0, \rd, c0, c5, 0
19 .macro busyuart, rd, rx
30 mov \rd, #0x2000000
32 subs \rd, \rd, #1
42 .macro senduart, rd, rx
46 .macro busyuart, rd, rx
57 mov \rd, #0x10000000
59 subs \rd, \rd, #1
85 mov \rd, #0x2000000
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A Dpl01x.S25 .macro senduart,rd,rx
26 strb \rd, [\rx, #UART01x_DR]
29 .macro waituartcts,rd,rx
32 .macro waituarttxrdy,rd,rx
33 1001: ldr \rd, [\rx, #UART01x_FR]
34 ARM_BE8( rev \rd, \rd )
35 tst \rd, #UART01x_FR_TXFF
39 .macro busyuart,rd,rx
40 1001: ldr \rd, [\rx, #UART01x_FR]
41 ARM_BE8( rev \rd, \rd )
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A Drenesas-scif.S36 .macro waituartcts,rd,rx
40 1001: ldrh \rd, [\rx, #FSR]
41 tst \rd, #TDFE
45 .macro senduart, rd, rx
46 strb \rd, [\rx, #FTDR]
47 ldrh \rd, [\rx, #FSR]
48 bic \rd, \rd, #TEND
49 strh \rd, [\rx, #FSR]
52 .macro busyuart, rd, rx
53 1001: ldrh \rd, [\rx, #FSR]
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A Dzynq.S32 .macro senduart,rd,rx
33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
36 .macro waituartcts,rd,rx
39 .macro waituarttxrdy,rd,rx
40 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
41 ARM_BE8( rev \rd, \rd )
42 tst \rd, #UART_SR_TXEMPTY
46 .macro busyuart,rd,rx
47 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
48 ARM_BE8( rev \rd, \rd )
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A Domap2plus.S63 .macro senduart,rd,rx
64 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
66 strb \rd, [\rx] @ send lower byte of rd
67 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
68 bic \rd, \rd, #(0xff << 24) @ restore original rd
71 .macro busyuart,rd,rx
72 1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
73 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
74 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
78 .macro waituartcts,rd,rx
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A Dimx.S33 .macro senduart,rd,rx
34 ARM_BE8(rev \rd, \rd)
35 str \rd, [\rx, #0x40] @ TXDATA
38 .macro waituartcts,rd,rx
41 .macro waituarttxrdy,rd,rx
44 .macro busyuart,rd,rx
45 1002: ldr \rd, [\rx, #0x98] @ SR2
46 ARM_BE8(rev \rd, \rd)
47 tst \rd, #1 << 3 @ TXDC
/linux/drivers/gpu/drm/msm/
A Dmsm_rd.c110 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open); in rd_write()
111 if (!rd->open) in rd_write()
229 if (!rd) in rd_cleanup()
233 kfree(rd); in rd_cleanup()
240 rd = kzalloc(sizeof(*rd), GFP_KERNEL); in rd_init()
241 if (!rd) in rd_init()
245 rd->fifo.buf = rd->buf; in rd_init()
254 return rd; in rd_init()
264 if (priv->rd) in msm_rd_debugfs_init()
273 priv->rd = rd; in msm_rd_debugfs_init()
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/linux/drivers/powercap/
A Dintel_rapl_common.c192 kfree(rd); in release_zone()
328 rp = rd->rp; in set_power_limit()
546 rd->rp = rp; in rapl_init_domains()
555 rd->id = i; in rapl_init_domains()
595 rd++; in rapl_init_domains()
709 if (prim == FW_LOCK && rd->rp->priv->limits[rd->id] == 2) { in rapl_read_data_raw()
1106 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { in rapl_package_register_powercap()
1130 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { in rapl_package_register_powercap()
1213 rd->rp->name, rd->name); in rapl_detect_powerlimit()
1255 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) in rapl_detect_domains()
[all …]
/linux/kernel/time/
A Dsched_clock.c91 cyc = (rd->read_sched_clock() - rd->epoch_cyc) & in sched_clock()
93 res = rd->epoch_ns + cyc_to_ns(cyc, rd->mult, rd->shift); in sched_clock()
112 cd.read_data[1] = *rd; in update_clock_read_data()
133 rd = cd.read_data[0]; in update_sched_clock()
136 ns = rd.epoch_ns + cyc_to_ns((cyc - rd.epoch_cyc) & rd.sched_clock_mask, rd.mult, rd.shift); in update_sched_clock()
138 rd.epoch_ns = ns; in update_sched_clock()
139 rd.epoch_cyc = cyc; in update_sched_clock()
177 rd = cd.read_data[0]; in sched_clock_register()
182 ns = rd.epoch_ns + cyc_to_ns((cyc - rd.epoch_cyc) & rd.sched_clock_mask, rd.mult, rd.shift); in sched_clock_register()
187 rd.mult = new_mult; in sched_clock_register()
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/linux/fs/jffs2/
A Dwrite.c231 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
265 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_write_dirent()
502 if (!rd) { in jffs2_do_create()
512 rd->totlen = cpu_to_je32(sizeof(*rd) + qstr->len); in jffs2_do_create()
521 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_do_create()
560 if (!rd) in jffs2_do_unlink()
575 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_do_unlink()
584 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_do_unlink()
677 if (!rd) in jffs2_do_link()
692 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_do_link()
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A Ddir.c389 if (!rd) { in jffs2_symlink()
401 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_symlink()
409 rd->type = DT_LNK; in jffs2_symlink()
410 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_symlink()
533 if (!rd) { in jffs2_mkdir()
545 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_mkdir()
553 rd->type = DT_DIR; in jffs2_mkdir()
554 rd->node_crc = cpu_to_je32(crc32(0, rd, sizeof(*rd)-8)); in jffs2_mkdir()
707 if (!rd) { in jffs2_mknod()
719 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_mknod()
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/linux/drivers/media/tuners/
A Dqt1010.c51 qt1010_i2c_oper_t rd[48] = { in qt1010_set_params() local
123 rd[2].val = reg05; in qt1010_set_params()
129 if (mod1 < 8000000) rd[6].val = 0x1d; in qt1010_set_params()
165 rd[35].val = (reg05 & 0xf0); in qt1010_set_params()
186 rd[43].val = priv->reg25_init_val; in qt1010_set_params()
195 freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \ in qt1010_set_params()
196 rd[8].val, rd[10].val, rd[13].val, rd[14].val, \ in qt1010_set_params()
197 rd[15].val, rd[35].val, rd[40].val, rd[41].val, \ in qt1010_set_params()
198 rd[43].val, rd[45].val); in qt1010_set_params()
201 if (rd[i].oper == QT1010_WR) { in qt1010_set_params()
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/linux/arch/sparc/include/asm/
A Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
73 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
79 rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
[all …]
/linux/drivers/reset/
A Dreset-pistachio.c66 struct pistachio_reset_data *rd; in pistachio_reset_assert() local
83 struct pistachio_reset_data *rd; in pistachio_reset_deassert() local
104 struct pistachio_reset_data *rd; in pistachio_reset_probe() local
108 rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL); in pistachio_reset_probe()
109 if (!rd) in pistachio_reset_probe()
113 if (IS_ERR(rd->periph_regs)) in pistachio_reset_probe()
114 return PTR_ERR(rd->periph_regs); in pistachio_reset_probe()
116 rd->rcdev.owner = THIS_MODULE; in pistachio_reset_probe()
117 rd->rcdev.nr_resets = PISTACHIO_RESET_MAX + 1; in pistachio_reset_probe()
118 rd->rcdev.ops = &pistachio_reset_ops; in pistachio_reset_probe()
[all …]
/linux/arch/arm/mach-tegra/
A Dsleep.h53 subne \rd, \rcpu, #1
54 movne \rd, \rd, lsl #3
55 addne \rd, \rd, #0x14
56 moveq \rd, #0
62 subne \rd, \rcpu, #1
63 movne \rd, \rd, lsl #3
64 addne \rd, \rd, #0x18
65 moveq \rd, #8
69 .macro cpu_id, rd
70 mrc p15, 0, \rd, c0, c0, 5
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A Dsleep-tegra30.S89 mov \rd, #1
106 biceq \rd, \rd, #\pll_mask
107 orrne \rd, \rd, #\pll_mask
116 biceq \rd, \rd, #PLLM_PMC_STORE_MASK
117 orrne \rd, \rd, #PLLM_PMC_STORE_MASK
126 orrne \rd, \rd, #(1 << 12)
136 orreq \rd, \rd, #(1 << 30)
141 bic \rd, \rd, #(1 << 18)
145 orr \rd, \rd, #(1 << 18)
163 bic \rd, \rd, #(1<<\iddq_bit)
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/linux/arch/arm/lib/
A Dio-writesb.S10 .macro outword, rd
12 strb \rd, [r0]
13 mov \rd, \rd, lsr #8
14 strb \rd, [r0]
15 mov \rd, \rd, lsr #8
16 strb \rd, [r0]
17 mov \rd, \rd, lsr #8
18 strb \rd, [r0]
20 mov lr, \rd, lsr #24
24 mov lr, \rd, lsr #8
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