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/linux/drivers/pinctrl/renesas/
A Dsh_pfc.h605 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
606 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
607 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
608 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
609 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
610 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
620 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
623 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx argument
662 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) argument
669 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
[all …]
A Dpfc-r8a73a4.c20 PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
21 PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
22 PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
23 PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
26 PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
27 PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
28 PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
30 PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
31 PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
32 PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
[all …]
A Dpfc-r8a779a0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \
49 PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
51 PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \
52 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
53 PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \
54 PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \
58 PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \
[all …]
A Dpfc-sh73a0.c19 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
21 PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
22 PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
23 PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
24 PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
26 PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
27 PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
29 PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
30 PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
32 PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
[all …]
A Dpfc-emev2.c12 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
13 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
14 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
15 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
16 PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
17 PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
18 PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
19 PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
20 PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
245 #define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0) argument
[all …]
A Dpfc-r8a7794.c17 #define CPU_ALL_GP(fn, sfx) \ argument
18 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_1(5, 7, fn, sfx), \
25 PORT_GP_1(5, 8, fn, sfx), \
26 PORT_GP_1(5, 9, fn, sfx), \
41 PORT_GP_1(5, 24, fn, sfx), \
42 PORT_GP_1(5, 25, fn, sfx), \
43 PORT_GP_1(5, 26, fn, sfx), \
[all …]
A Dpfc-r8a77470.c13 #define CPU_ALL_GP(fn, sfx) \ argument
14 PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15 PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
34 PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
35 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
36 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
37 PORT_GP_CFG_1(3, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
40 PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
[all …]
/linux/arch/arm64/include/asm/
A Dcmpxchg.h30 "1: ld" #acq "xr" #sfx "\t%" #w "0, %2\n" \
64 #define __XCHG_GEN(sfx) \ argument
71 return __xchg_case##sfx##_8(x, ptr); \
73 return __xchg_case##sfx##_16(x, ptr); \
75 return __xchg_case##sfx##_32(x, ptr); \
77 return __xchg_case##sfx##_64(x, ptr); \
92 #define __xchg_wrapper(sfx, ptr, x) \ argument
150 #define __CMPXCHG_GEN(sfx) \ argument
232 #define __CMPWAIT_CASE(w, sfx, sz) \ argument
241 " ldxr" #sfx "\t%" #w "[tmp], %[v]\n" \
[all …]
A Drwonce.h16 #define __LOAD_RCPC(sfx, regs...) \ argument
18 "ldar" #sfx "\t" #regs, \
20 "ldapr" #sfx "\t" #regs, \
23 #define __LOAD_RCPC(sfx, regs...) "ldar" #sfx "\t" #regs argument
A Dpercpu.h65 #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ argument
74 "1: ldxr" #sfx "\t%" #w "[tmp], %[ptr]\n" \
76 " stxr" #sfx "\t%w[loop], %" #w "[tmp], %[ptr]\n" \
86 #define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ argument
95 "1: ldxr" #sfx "\t%" #w "[ret], %[ptr]\n" \
97 " stxr" #sfx "\t%w[loop], %" #w "[ret], %[ptr]\n" \
/linux/scripts/atomic/
A Dgen-atomic-fallback.sh15 local sfx="$1"; shift
20 local atomicname="arch_${atomic}_${pfx}${name}${sfx}${order}"
41 local sfx="$1"; shift
64 local sfx="$1"; shift
68 local basename="arch_${atomic}_${pfx}${name}${sfx}"
79 local sfx="$1"; shift
82 local basename="arch_${atomic}_${pfx}${name}${sfx}"
89 gen_proto_fallback "${meta}" "${pfx}" "${name}" "${sfx}" "" "$@"
112 gen_proto_fallback "${meta}" "${pfx}" "${name}" "${sfx}" "" "$@"
113 gen_proto_fallback "${meta}" "${pfx}" "${name}" "${sfx}" "_acquire" "$@"
[all …]
A Datomic-tbl.sh44 local sfx="$1"; shift
55 for base in "${pfx}${name}${sfx}${order}" "${name}"; do
151 local sfx="$1"; shift
153 gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "" "$@"
156 gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "_acquire" "$@"
159 gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "_release" "$@"
162 gen_proto_order_variant "${meta}" "${pfx}" "${name}" "${sfx}" "_relaxed" "$@"
172 local sfx=""
175 meta_in "${meta}" "R" && sfx="_return"
177 gen_proto_order_variants "${meta}" "${pfx}" "${name}" "${sfx}" "$@"
/linux/tools/testing/selftests/netfilter/
A Dnft_nat_zones.sh34 sfx=$(mktemp -u "XXXXXXXX")
35 gw="ns-gw-$sfx"
36 cl1="ns-cl1-$sfx"
37 cl2="ns-cl2-$sfx"
38 srv="ns-srv-$sfx"
52 ip netns del ns-cl$i-$sfx 2>/dev/null
114 cl="ns-cl$i-$sfx"
129 cl="ns-cl$i-$sfx"
228 cl="ns-cl$i-$sfx"
276 cl="ns-cl$i-$sfx"
A Dnf_nat_edemux.sh11 sfx=$(mktemp -u "XXXXXXXX")
12 ns1="ns1-$sfx"
13 ns2="ns2-$sfx"
A Dnft_nat.sh11 sfx=$(mktemp -u "XXXXXXXX")
12 ns0="ns0-$sfx"
13 ns1="ns1-$sfx"
14 ns2="ns2-$sfx"
18 for i in 0 1 2; do ip netns del ns$i-"$sfx";done
70 ip -net ns$i-$sfx link set lo up
71 ip -net ns$i-$sfx link set eth0 up
72 ip -net ns$i-$sfx addr add 10.0.$i.99/24 dev eth0
73 ip -net ns$i-$sfx route add default via 10.0.$i.1
74 ip -net ns$i-$sfx addr add dead:$i::99/64 dev eth0
[all …]
A Dnft_conntrack_helper.sh11 sfx=$(mktemp -u "XXXXXXXX")
12 ns1="ns1-$sfx"
13 ns2="ns2-$sfx"
A Dnft_fib.sh9 sfx=$(mktemp -u "XXXXXXXX")
10 ns1="ns1-$sfx"
11 ns2="ns2-$sfx"
12 nsrouter="nsrouter-$sfx"
A Dconntrack_tcp_unreplied.sh12 sfx=$(mktemp -u "XXXXXXXX")
13 ns1="ns1-$sfx"
14 ns2="ns2-$sfx"
/linux/include/linux/
A Dbtree-type.h2 #define __BTREE_TP(pfx, type, sfx) pfx ## type ## sfx argument
3 #define _BTREE_TP(pfx, type, sfx) __BTREE_TP(pfx, type, sfx) argument
/linux/scripts/atomic/fallbacks/
A Drelease3 arch_${atomic}_${pfx}${name}${sfx}_release(${params})
6 ${retstmt}arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});
A Ddec3 arch_${atomic}_${pfx}dec${sfx}${order}(${atomic}_t *v)
5 ${retstmt}arch_${atomic}_${pfx}sub${sfx}${order}(1, v);
A Dinc3 arch_${atomic}_${pfx}inc${sfx}${order}(${atomic}_t *v)
5 ${retstmt}arch_${atomic}_${pfx}add${sfx}${order}(1, v);
A Dacquire3 arch_${atomic}_${pfx}${name}${sfx}_acquire(${params})
5 ${ret} ret = arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});
A Dandnot3 arch_${atomic}_${pfx}andnot${sfx}${order}(${int} i, ${atomic}_t *v)
5 ${retstmt}arch_${atomic}_${pfx}and${sfx}${order}(~i, v);
A Dfence3 arch_${atomic}_${pfx}${name}${sfx}(${params})
7 ret = arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});

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