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Searched refs:AMDGPU_GPU_PAGE_ALIGN (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_vcn.c220 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_vcn_sw_init()
221 bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
236 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
238 bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
548 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_send_msg()
602 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_create_msg()
637 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_destroy_msg()
692 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_sw_send_msg()
815 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_create_msg()
869 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_destroy_msg()
A Damdgpu_gart.h38 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) macro
A Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
A Dvcn_v2_5.c382 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume()
431 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_5_mc_resume()
437 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
524 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1181 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_sriov_start()
A Dvcn_v2_0.c323 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume()
372 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_0_mc_resume()
379 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
466 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1871 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_start_sriov()
A Dvcn_v3_0.c432 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume()
477 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v3_0_mc_resume()
482 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
569 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1316 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_start_sriov()
A Dvcn_v1_0.c296 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_spg_mode()
363 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_dpg_mode()
A Damdgpu_vce.c468 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); in amdgpu_vce_get_create_msg()
A Damdgpu_uvd.c327 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_uvd_sw_init()
A Duvd_v7_0.c815 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v7_0_sriov_start()
A Damdgpu_vm.c256 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); in amdgpu_vm_bo_size()

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