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Searched refs:AR_PHY_AGC_CONTROL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/net/wireless/ath/ath9k/
A Dcalib.c234 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
238 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
241 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
244 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
254 u32 bb_agc_ctl = REG_READ(ah, AR_PHY_AGC_CONTROL); in ath9k_hw_loadnf()
298 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
300 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
312 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & in ath9k_hw_loadnf()
324 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
327 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
[all …]
A Dar9003_calib.c349 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
353 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
370 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
374 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
376 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
390 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
534 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
1492 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_init_cal_pcoem()
1493 REG_READ(ah, AR_PHY_AGC_CONTROL) | in ar9003_hw_init_cal_pcoem()
1565 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in do_ar9003_agc_cal()
[all …]
A Dar9002_calib.c755 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
758 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
759 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
771 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
773 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
784 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
860 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
865 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
866 REG_READ(ah, AR_PHY_AGC_CONTROL) | in ar9002_hw_init_cal()
870 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
[all …]
A Dar9003_phy.c299 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
317 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
A Dreg.h2117 #define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AG… macro

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