Home
last modified time | relevance | path

Searched refs:AVIVO_D1GRPH_UPDATE (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Drs600.c123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
160 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
A Drv515.c336 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_stop()
339 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_stop()
386 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
389 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_resume()
397 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
A Drv770.c814 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
819 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
842 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
850 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
858 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
A Dr500_reg.h419 #define AVIVO_D1GRPH_UPDATE 0x6144 macro

Completed in 15 milliseconds