Searched refs:B0_XA_CSR (Results 1 – 3 of 3) sorted by relevance
317 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ; in init_tx()969 outpd(ADDR(B0_XA_CSR),CSR_SET_RESET) ; in init_mac()973 outpd(ADDR(B0_XA_CSR),CSR_CLR_RESET) ; in init_mac()
562 outpd(ADDR(B0_XA_CSR),CSR_START) ; in mac_drv_repair_descr()1655 outpd(ADDR(B0_XA_CSR),CSR_START) ; in hwm_tx_frag()1895 outpd(ADDR(B0_XA_CSR),CSR_START) ; in smt_send_mbuf()
83 #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ macro
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