| /linux/drivers/net/ethernet/smsc/ |
| A D | smc91c92_cs.c | 1038 save = inw(ioaddr + BANK_SELECT); in smc_dump()
1046 outw(save, ioaddr + BANK_SELECT); in smc_dump()
1091 dev->name, inw(ioaddr + BANK_SELECT)); in smc_close()
1363 saved_bank = inw(ioaddr + BANK_SELECT); in smc_interrupt()
1621 saved_bank = inw(ioaddr + BANK_SELECT); in smc_set_xcvr()
1725 saved_bank = inw(ioaddr + BANK_SELECT); in media_check()
1765 saved_bank = inw(ioaddr + BANK_SELECT); in media_check()
1921 u16 saved_bank = inw(ioaddr + BANK_SELECT); in smc_get_link_ksettings()
1940 u16 saved_bank = inw(ioaddr + BANK_SELECT); in smc_set_link_ksettings()
1959 u16 saved_bank = inw(ioaddr + BANK_SELECT); in smc_get_link()
[all …]
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| A D | smc9194.h | 60 #define BANK_SELECT 14 macro
204 #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
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| A D | smc9194.c | 868 bank = inw( ioaddr + BANK_SELECT ); in smc_probe()
875 outw( 0x0, ioaddr + BANK_SELECT ); in smc_probe()
876 bank = inw( ioaddr + BANK_SELECT ); in smc_probe()
1327 saved_bank = inw( ioaddr + BANK_SELECT ); in smc_interrupt()
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| A D | smc91x.h | 484 #define BANK_SELECT (14 << SMC_IO_SHIFT) macro
927 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
934 SMC_outw(lp, x, ioaddr, BANK_SELECT); \
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | gfxhub_v1_0.c | 195 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v1_0_init_cache_regs()
199 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v1_0_init_cache_regs()
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| A D | gfxhub_v2_0.c | 234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v2_0_init_cache_regs()
238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v2_0_init_cache_regs()
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| A D | gfxhub_v2_1.c | 237 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); in gfxhub_v2_1_init_cache_regs()
241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); in gfxhub_v2_1_init_cache_regs()
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| A D | mmhub_v2_0.c | 307 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v2_0_init_cache_regs()
311 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v2_0_init_cache_regs()
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| A D | mmhub_v2_3.c | 228 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v2_3_init_cache_regs()
232 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v2_3_init_cache_regs()
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| A D | mmhub_v1_0.c | 180 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_0_init_cache_regs()
184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_0_init_cache_regs()
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| A D | mmhub_v1_7.c | 201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v1_7_init_cache_regs()
205 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v1_7_init_cache_regs()
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| A D | mmhub_v9_4.c | 235 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v9_4_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v9_4_init_cache_regs()
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| A D | gmc_v7_0.c | 654 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
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| A D | gmc_v8_0.c | 872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
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| A D | sid.h | 387 #define BANK_SELECT(x) ((x) << 0) macro
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| /linux/drivers/net/ethernet/microchip/ |
| A D | encx24j600_hw.h | 22 #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1)) macro
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| A D | encx24j600-regmap.c | 24 int bank_opcode = BANK_SELECT(bank); in encx24j600_switch_bank()
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| /linux/drivers/gpu/drm/radeon/ |
| A D | rv770.c | 921 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
967 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
998 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
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| A D | rv770d.h | 651 #define BANK_SELECT(x) ((x) << 0) macro
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| A D | nid.h | 121 #define BANK_SELECT(x) ((x) << 0) macro
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| A D | sid.h | 386 #define BANK_SELECT(x) ((x) << 0) macro
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| A D | cikd.h | 504 #define BANK_SELECT(x) ((x) << 0) macro
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| A D | evergreen.c | 2415 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2468 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2498 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
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| A D | evergreend.h | 1159 #define BANK_SELECT(x) ((x) << 0) macro
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| A D | ni.c | 1289 BANK_SELECT(6) | in cayman_pcie_gart_enable()
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