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Searched refs:BIT1 (Results 1 – 25 of 56) sorted by relevance

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/linux/drivers/staging/rtl8723bs/include/
A Dhal_pwr_seq.h50 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x…
58 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable fallin…
59 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 …
62 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR …
73 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 …
96 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s…
116 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s…
164 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] =…
188 …PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA…
202 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] =…
[all …]
A Dhal_com_reg.h609 #define RRSR_2M BIT1
634 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
786 #define IMR_OCPINT BIT1
841 #define PHIMR_OCPINT BIT1
894 #define UHIMR_OCPINT BIT1
986 #define StopVI BIT1
1540 #define SDIO_HIMR_AVAL_MSK BIT1
1566 #define SDIO_HISR_AVAL BIT1
1606 #define HCI_RESUME_PWR_RDY BIT1
1657 #define HAL92C_EN_PKT_LIFE_TIME_VI BIT1
[all …]
A Drtw_ht.h65 #define LDPC_HT_ENABLE_TX BIT1
70 #define STBC_HT_ENABLE_TX BIT1
75 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
A Dhal_phy.h14 #define ANT_DETECT_BY_RSSI BIT1
A Drtl8723b_spec.h213 #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
A Dosdep_service.h18 #define BIT1 0x00000002 macro
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
A Dpwrseq.h29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
392 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
423 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
435 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
459 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
505 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
546 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
[all …]
/linux/drivers/scsi/
A Ddc395x.h75 #define BIT1 0x00000002 macro
80 #define UNIT_INFO_CHANGED BIT1
86 #define SCSI_SUPPORT BIT1
122 #define RESET_DETECT BIT1
130 #define ABORTION BIT1
142 #define ABORT_DEV BIT1
166 #define SYNC_NEGO_DONE BIT1
593 #define GREATER_1G BIT1
/linux/drivers/staging/rtl8192e/rtl8192e/
A Dr8192E_hw.h130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
148 #define RCR_APM BIT1
202 #define SCR_RxUseDK BIT1
227 #define IMR_VODOK BIT1
232 #define TPPoll_BEQ BIT1
272 #define AcmHw_BeqEn BIT1
280 #define AcmFw_ViqStatus BIT1
333 #define BW_OPMODE_5G BIT1
362 #define RRSR_2M BIT1
/linux/drivers/video/fbdev/via/
A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
A Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
606 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
672 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
A Dvia_utility.c170 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
A Dshare.h15 #define BIT1 0x02 macro
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
A Dhalbt_precomp.h32 #define BIT1 0x00000002 macro
A Dhalbtc8192e2ant.h13 #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
A Dhalbtc8821a1ant.h14 #define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
A Dhalbtc8821a2ant.h14 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
A Dhalbtc8723b2ant.h16 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
/linux/drivers/tty/
A Dsynclink_gt.c355 #define MASK_PARITY BIT1
1788 if (status & BIT1) in rx_async()
1795 if (status & BIT1) in rx_async()
1973 if (status & BIT1) { in dcd_change()
3797 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3810 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
4331 val |= BIT1 + BIT0; in sync_mode()
4441 if (status & BIT1) in get_gtsignals()
4483 val |= BIT1; in msc_set_vcr()
4599 status &= ~BIT1; in rx_get_frame()
[all …]
/linux/drivers/staging/rtl8723bs/hal/
A DHalHWImg8723B_MAC.c58 if ((cond1 & BIT1) != 0) /* GPA */ in CheckPositive()
A DHalBtc8723b2Ant.h14 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
A Dodm_DIG.h82 ODM_RESUME_DIG = BIT1
A DHalBtc8723b1Ant.h14 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
A DHalHWImg8723B_RF.c64 if ((cond1 & BIT1) != 0) /* GPA */ in CheckPositive()
/linux/drivers/staging/rtl8192e/
A Drtl819x_Qos.h11 #define BIT1 0x00000002 macro

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