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Searched refs:BIT18 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/staging/rtl8723bs/include/
A Dhal_com_reg.h626 #define RRSR_MCS6 BIT18
758 #define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK Interrupt 1 */
806 #define PHIMR_BCNDOK2 BIT18
832 #define PHIMR_BCNDOK6 BIT18
857 #define UHIMR_BCNDOK2 BIT18
883 #define UHIMR_BCNDOK6 BIT18
941 #define IMR_BCNDOK5_88E BIT18 /* Beacon Queue DMA OK Interrupt 5 */
1005 #define RCR_TIM_PARSER_EN BIT18 /* RX Beacon TIM Parser. */
1549 #define SDIO_HIMR_CPWM1_MSK BIT18
1575 #define SDIO_HISR_CPWM1 BIT18
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A Drtl8723b_spec.h226 #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */
A Dosdep_service.h35 #define BIT18 0x00040000 macro
/linux/drivers/staging/rtl8192e/rtl8192e/
A Dr8192E_hw.h131 BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)
142 #define RCR_ADF BIT18
379 #define RRSR_MCS6 BIT18
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
A Dhalbt_precomp.h49 #define BIT18 0x00040000 macro
/linux/drivers/staging/rtl8192e/
A Drtl819x_Qos.h28 #define BIT18 0x00040000 macro
/linux/include/uapi/linux/
A Dsynclink.h37 #define BIT18 0x00040000 macro
/linux/drivers/staging/rtl8723bs/hal/
A DHal8723BReg.h415 #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */
A Dhal_com.c1208 PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target); in rtw_bb_rf_gain_offset()
/linux/drivers/scsi/
A Ddc395x.h58 #define BIT18 0x00040000 macro
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
A Dreg.h376 #define RRSR_MCS6 BIT18
/linux/drivers/scsi/lpfc/
A Dlpfc_hw4.h750 #define LPFC_SLI4_INTR18 BIT18

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