| /linux/drivers/scsi/ |
| A D | dc395x.h | 74 #define BIT2 0x00000004 macro
81 #define FORMATING_MEDIA BIT2
87 #define ASPI_SUPPORT BIT2
123 #define RESET_DONE BIT2
131 #define OVER_RUN BIT2
141 #define RESET_DEV0 BIT2
167 #define WIDE_NEGO_ENABLE BIT2
594 #define RST_SCSI_BUS BIT2
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| /linux/drivers/staging/rtl8192e/rtl8192e/ |
| A D | r8192E_hw.h | 130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
147 #define RCR_AM BIT2
203 #define SCR_TxEncEnable BIT2
226 #define IMR_VIDOK BIT2
233 #define TPPoll_VIQ BIT2
273 #define AcmHw_ViqEn BIT2
281 #define AcmFw_VoqStatus BIT2
334 #define BW_OPMODE_20MHZ BIT2
363 #define RRSR_5_5M BIT2
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| /linux/drivers/staging/rtl8723bs/include/ |
| A D | hal_com_reg.h | 610 #define RRSR_5_5M BIT2
635 #define HAL92C_WOL_DISASSOC_EVENT BIT2
700 #define BW_OPMODE_20MHZ BIT2
733 #define WOW_MAGIC BIT2 /* Magic packet */
927 #define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */
985 #define StopBE BIT2
1541 #define SDIO_HIMR_TXERR_MSK BIT2
1567 #define SDIO_HISR_TXERR BIT2
1656 #define HAL92C_EN_PKT_LIFE_TIME_BE BIT2
1667 #define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2)
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| A D | rtw_ht.h | 66 #define LDPC_HT_TEST_TX_ENABLE BIT2
71 #define STBC_HT_TEST_TX_ENABLE BIT2
76 #define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target suppo…
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| A D | hal_pwr_seq.h | 48 …AB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW …
105 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1…
183 …_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
208 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/…
210 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/…
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| A D | rtl8723b_spec.h | 212 #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
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| A D | osdep_service.h | 19 #define BIT2 0x00000004 macro
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| /linux/drivers/video/fbdev/via/ |
| A D | dvi.c | 335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
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| A D | lcd.c | 345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
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| A D | share.h | 16 #define BIT2 0x04 macro
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| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| A D | pwrseq.h | 26 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
523 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
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| /linux/drivers/staging/rtl8723bs/hal/ |
| A D | HalHWImg8723B_MAC.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
60 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
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| A D | HalHWImg8723B_RF.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
66 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
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| A D | HalHWImg8723B_BB.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
61 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
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| A D | HalBtc8723b2Ant.h | 13 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
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| A D | HalBtc8723b1Ant.h | 13 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
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| /linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| A D | halbt_precomp.h | 33 #define BIT2 0x00000004 macro
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| A D | halbtcoutsrc.h | 89 #define INTF_NOTIFY BIT2
94 #define ALGO_BT_MONITOR BIT2
106 #define WIFI_HS_CONNECTED BIT2
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| A D | halbtc8192e2ant.h | 12 #define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
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| A D | halbtc8821a1ant.h | 13 #define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
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| A D | halbtc8821a2ant.h | 13 #define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
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| A D | halbtc8723b2ant.h | 15 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
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| /linux/drivers/char/pcmcia/ |
| A D | synclink_cs.c | 308 #define CEC BIT2 // command executing
313 #define PVR_RI BIT2
1190 if (gis & (BIT3 | BIT2)) in mgslpc_isr()
1237 if (pis & BIT2) in mgslpc_isr()
2915 val |= BIT2; in enable_auxclk()
3058 val |= BIT2; in hdlc_mode()
3081 val |= BIT4 | BIT2; in hdlc_mode()
3141 val |= BIT2 | BIT1; in hdlc_mode()
3483 val |= BIT2; /* Parity enable */ in async_mode()
3592 val |= BIT2; in set_signals()
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| /linux/drivers/tty/ |
| A D | synclink_gt.c | 193 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
1938 if (status & BIT2) { in cts_change()
3922 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
3925 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
3971 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
4191 val = BIT2; in sync_mode()
4328 val |= BIT2; /* 001, rxclk = TXC Input */ in sync_mode()
4439 if (status & BIT2) in get_gtsignals()
4481 val |= BIT2; in msc_set_vcr()
4500 val |= BIT2; in set_gtsignals()
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| /linux/drivers/staging/rtl8192e/ |
| A D | rtl819x_Qos.h | 12 #define BIT2 0x00000004 macro
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