| /linux/drivers/staging/rtl8192e/rtl8192e/ |
| A D | r8192E_hw.h | 100 #define EPROM_CMD_RESERVED_MASK BIT5
130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
145 #define RCR_ACRC32 BIT5
182 #define CAM_USEDK BIT5
206 #define SCR_NoSKMC BIT5
223 #define IMR_HCCADOK BIT5
236 #define TPPoll_CQ BIT5
276 #define AcmHw_ViqStatus BIT5
366 #define RRSR_9M BIT5
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| /linux/drivers/scsi/ |
| A D | dc395x.h | 71 #define BIT5 0x00000020 macro
134 #define SRB_ERROR BIT5
139 #define RESIDUAL_VALID BIT5
170 #define EN_TAG_QUEUEING BIT5
597 #define LUN_CHECK BIT5
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| /linux/drivers/staging/rtl8723bs/include/ |
| A D | hal_com_reg.h | 539 #define GPIOSEL_ENBT BIT5
561 #define HSIMR_SPS_OCP_INT_EN BIT5
570 #define HSISR_SPS_OCP_INT BIT5
613 #define RRSR_9M BIT5
707 #define CAM_USEDK BIT5
870 #define UHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */
924 #define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */
982 #define StopHigh BIT5
1544 #define SDIO_HIMR_RXFOVW_MSK BIT5
1570 #define SDIO_HISR_RXFOVW BIT5
[all …]
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| A D | hal_pwr_seq.h | 47 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b…
76 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b…
151 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK …
182 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TS…
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| A D | rtl8723b_spec.h | 170 #define BIT_BCN_PORT_SEL BIT5
209 #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
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| A D | osdep_service.h | 22 #define BIT5 0x00000020 macro
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| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| A D | pwrseq.h | 262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
383 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
619 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
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| /linux/drivers/video/fbdev/via/ |
| A D | dvi.c | 62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
408 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
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| A D | hw.c | 1696 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1702 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1713 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1717 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1720 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1725 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2065 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); in viafb_set_dpa_gfx()
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| A D | share.h | 19 #define BIT5 0x20 macro
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| /linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| A D | halbt_precomp.h | 36 #define BIT5 0x00000020 macro
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| A D | halbtc8192e2ant.h | 9 #define BT_INFO_8192E_2ANT_B_HID BIT5
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| A D | halbtc8821a1ant.h | 10 #define BT_INFO_8821A_1ANT_B_HID BIT5
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| A D | halbtc8821a2ant.h | 10 #define BT_INFO_8821A_2ANT_B_HID BIT5
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| A D | halbtc8723b2ant.h | 12 #define BT_INFO_8723B_2ANT_B_HID BIT5
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| A D | halbtc8723b1ant.h | 9 #define BT_INFO_8723B_1ANT_B_HID BIT5
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| /linux/drivers/staging/rtl8723bs/hal/ |
| A D | HalBtc8723b2Ant.h | 10 #define BT_INFO_8723B_2ANT_B_HID BIT5
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| A D | HalBtc8723b1Ant.h | 10 #define BT_INFO_8723B_1ANT_B_HID BIT5
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| A D | Hal8723BReg.h | 398 #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
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| A D | odm.h | 371 ODM_BB_CCK_PD = BIT5,
448 ODM_WM_AUTO = BIT5,
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| /linux/drivers/staging/rtl8192e/ |
| A D | rtl819x_Qos.h | 15 #define BIT5 0x00000020 macro
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| /linux/drivers/tty/ |
| A D | synclink_gt.c | 395 #define IRQ_DCD BIT5
2138 if (status & (BIT5 + BIT4)) { in isr_rdma()
2163 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4062 case 7: val |= BIT5; break; in async_mode()
4063 case 8: val |= BIT5 + BIT4; break; in async_mode()
4102 case 7: val |= BIT5; break; in async_mode()
4103 case 8: val |= BIT5 + BIT4; break; in async_mode()
4399 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; in tx_set_idle()
4404 tcr &= ~(BIT5 + BIT4); in tx_set_idle()
4466 val |= BIT5; /* 0010 */ in msc_set_vcr()
[all …]
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| /linux/include/uapi/linux/ |
| A D | synclink.h | 24 #define BIT5 0x0020 macro
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| /linux/drivers/char/pcmcia/ |
| A D | synclink_cs.c | 678 #define CMD_RXFIFO_READ BIT5
906 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5)) in rx_ready_async()
2991 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3118 val |= BIT5; in hdlc_mode()
3143 val |= BIT5; in hdlc_mode()
3206 val |= BIT5; in hdlc_mode()
3480 val |= BIT5; in async_mode()
3523 val |= BIT5; in async_mode()
3648 else if (!(status & BIT5)) { in rx_get_frame()
3679 if (status & BIT5) in rx_get_frame()
[all …]
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| /linux/lib/zstd/common/ |
| A D | zstd_internal.h | 142 #define BIT5 32 macro
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