Searched refs:BIT8 (Results 1 – 18 of 18) sorted by relevance
| /linux/drivers/staging/rtl8723bs/include/ |
| A D | hal_com_reg.h | 616 #define RRSR_24M BIT8
768 #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */
784 #define IMR_CPWM BIT8
816 #define PHIMR_CPWM BIT8
839 #define PHIMR_RXFOVW BIT8
867 #define UHIMR_CPWM BIT8
892 #define UHIMR_RXFOVW BIT8
921 #define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
950 #define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */
1015 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
|
| A D | rtl8723b_spec.h | 206 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
235 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
|
| A D | osdep_service.h | 25 #define BIT8 0x00000100 macro
|
| A D | rtw_mlme_ext.h | 52 #define DYNAMIC_BB_PWR_TRAIN BIT8 /* ODM_BB_PWR_TRAIN */
|
| /linux/drivers/staging/rtl8192e/rtl8192e/ |
| A D | r8192E_hw.h | 220 #define IMR_HIGHDOK BIT8
239 #define TPPoll_HCCAQ BIT8
369 #define RRSR_24M BIT8
|
| /linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| A D | halbt_precomp.h | 39 #define BIT8 0x00000100 macro
|
| A D | halbtcoutsrc.h | 100 #define ALGO_TRACE_SW_DETAIL BIT8
|
| /linux/drivers/staging/rtl8723bs/hal/ |
| A D | Hal8723BReg.h | 395 #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
424 #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
|
| A D | rtl8723b_phycfg.c | 133 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
135 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
|
| A D | odm.h | 374 ODM_BB_PWR_TRAIN = BIT8,
400 ODM_RTL8723B = BIT8,
|
| A D | odm_DIG.c | 22 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 … in odm_NHMCounterStatisticsInit()
|
| /linux/drivers/staging/rtl8192e/ |
| A D | rtl819x_Qos.h | 18 #define BIT8 0x00000100 macro
|
| /linux/include/uapi/linux/ |
| A D | synclink.h | 27 #define BIT8 0x0100 macro
|
| /linux/drivers/scsi/ |
| A D | dc395x.h | 68 #define BIT8 0x00000100 macro
|
| /linux/drivers/tty/ |
| A D | synclink_gt.c | 392 #define IRQ_RXOVER BIT8
2288 if (gsr & (BIT8 << i)) in slgt_interrupt()
4056 val |= BIT8; in async_mode()
4096 val |= BIT8; in async_mode()
4145 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && in async_mode()
4218 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4291 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4934 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
|
| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/ |
| A D | reg.h | 366 #define RRSR_24M BIT8
|
| /linux/drivers/scsi/lpfc/ |
| A D | lpfc_hw4.h | 740 #define LPFC_SLI4_INTR8 BIT8
|
| /linux/drivers/char/pcmcia/ |
| A D | synclink_cs.c | 297 #define IRQ_TXFIFO BIT8 // transmit pool ready
|
Completed in 84 milliseconds