1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2011-2014 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 */
6
7 #include <linux/clk/imx.h>
8 #include <linux/delay.h>
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/irq.h>
12 #include <linux/genalloc.h>
13 #include <linux/irqchip/arm-gic.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/regmap.h>
20 #include <linux/suspend.h>
21 #include <asm/cacheflush.h>
22 #include <asm/fncpy.h>
23 #include <asm/proc-fns.h>
24 #include <asm/suspend.h>
25 #include <asm/tlb.h>
26
27 #include "common.h"
28 #include "hardware.h"
29
30 #define CCR 0x0
31 #define BM_CCR_WB_COUNT (0x7 << 16)
32 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
33 #define BM_CCR_RBC_EN (0x1 << 27)
34
35 #define CLPCR 0x54
36 #define BP_CLPCR_LPM 0
37 #define BM_CLPCR_LPM (0x3 << 0)
38 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
39 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
40 #define BM_CLPCR_SBYOS (0x1 << 6)
41 #define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
42 #define BM_CLPCR_VSTBY (0x1 << 8)
43 #define BP_CLPCR_STBY_COUNT 9
44 #define BM_CLPCR_STBY_COUNT (0x3 << 9)
45 #define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
46 #define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
47 #define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
48 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
49 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
50 #define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
51 #define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
52 #define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
53 #define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
54 #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
55 #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
56
57 #define CGPR 0x64
58 #define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
59
60 #define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
61 #define MX6_MAX_MMDC_IO_NUM 33
62
63 static void __iomem *ccm_base;
64 static void __iomem *suspend_ocram_base;
65 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
66
67 /*
68 * suspend ocram space layout:
69 * ======================== high address ======================
70 * .
71 * .
72 * .
73 * ^
74 * ^
75 * ^
76 * imx6_suspend code
77 * PM_INFO structure(imx6_cpu_pm_info)
78 * ======================== low address =======================
79 */
80
81 struct imx6_pm_base {
82 phys_addr_t pbase;
83 void __iomem *vbase;
84 };
85
86 struct imx6_pm_socdata {
87 u32 ddr_type;
88 const char *mmdc_compat;
89 const char *src_compat;
90 const char *iomuxc_compat;
91 const char *gpc_compat;
92 const char *pl310_compat;
93 const u32 mmdc_io_num;
94 const u32 *mmdc_io_offset;
95 };
96
97 static const u32 imx6q_mmdc_io_offset[] __initconst = {
98 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
99 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
100 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
101 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
102 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
103 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
104 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
105 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
106 0x74c, /* GPR_ADDS */
107 };
108
109 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
110 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
111 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
112 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
113 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
114 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
115 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
116 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
117 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
118 0x74c, /* GPR_ADDS */
119 };
120
121 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
122 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
123 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
124 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
125 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
126 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
127 };
128
129 static const u32 imx6sll_mmdc_io_offset[] __initconst = {
130 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
131 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
132 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
133 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/
134 };
135
136 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
137 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
138 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
139 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
140 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
141 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
142 };
143
144 static const u32 imx6ul_mmdc_io_offset[] __initconst = {
145 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
146 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
147 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
148 0x494, 0x4b0, /* MODE_CTL, MODE, */
149 };
150
151 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
152 .mmdc_compat = "fsl,imx6q-mmdc",
153 .src_compat = "fsl,imx6q-src",
154 .iomuxc_compat = "fsl,imx6q-iomuxc",
155 .gpc_compat = "fsl,imx6q-gpc",
156 .pl310_compat = "arm,pl310-cache",
157 .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
158 .mmdc_io_offset = imx6q_mmdc_io_offset,
159 };
160
161 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
162 .mmdc_compat = "fsl,imx6q-mmdc",
163 .src_compat = "fsl,imx6q-src",
164 .iomuxc_compat = "fsl,imx6dl-iomuxc",
165 .gpc_compat = "fsl,imx6q-gpc",
166 .pl310_compat = "arm,pl310-cache",
167 .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
168 .mmdc_io_offset = imx6dl_mmdc_io_offset,
169 };
170
171 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
172 .mmdc_compat = "fsl,imx6sl-mmdc",
173 .src_compat = "fsl,imx6sl-src",
174 .iomuxc_compat = "fsl,imx6sl-iomuxc",
175 .gpc_compat = "fsl,imx6sl-gpc",
176 .pl310_compat = "arm,pl310-cache",
177 .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
178 .mmdc_io_offset = imx6sl_mmdc_io_offset,
179 };
180
181 static const struct imx6_pm_socdata imx6sll_pm_data __initconst = {
182 .mmdc_compat = "fsl,imx6sll-mmdc",
183 .src_compat = "fsl,imx6sll-src",
184 .iomuxc_compat = "fsl,imx6sll-iomuxc",
185 .gpc_compat = "fsl,imx6sll-gpc",
186 .pl310_compat = "arm,pl310-cache",
187 .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset),
188 .mmdc_io_offset = imx6sll_mmdc_io_offset,
189 };
190
191 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
192 .mmdc_compat = "fsl,imx6sx-mmdc",
193 .src_compat = "fsl,imx6sx-src",
194 .iomuxc_compat = "fsl,imx6sx-iomuxc",
195 .gpc_compat = "fsl,imx6sx-gpc",
196 .pl310_compat = "arm,pl310-cache",
197 .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
198 .mmdc_io_offset = imx6sx_mmdc_io_offset,
199 };
200
201 static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
202 .mmdc_compat = "fsl,imx6ul-mmdc",
203 .src_compat = "fsl,imx6ul-src",
204 .iomuxc_compat = "fsl,imx6ul-iomuxc",
205 .gpc_compat = "fsl,imx6ul-gpc",
206 .pl310_compat = NULL,
207 .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
208 .mmdc_io_offset = imx6ul_mmdc_io_offset,
209 };
210
211 /*
212 * This structure is for passing necessary data for low level ocram
213 * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
214 * definition is changed, the offset definition in
215 * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
216 * otherwise, the suspend to ocram function will be broken!
217 */
218 struct imx6_cpu_pm_info {
219 phys_addr_t pbase; /* The physical address of pm_info. */
220 phys_addr_t resume_addr; /* The physical resume address for asm code */
221 u32 ddr_type;
222 u32 pm_info_size; /* Size of pm_info. */
223 struct imx6_pm_base mmdc_base;
224 struct imx6_pm_base src_base;
225 struct imx6_pm_base iomuxc_base;
226 struct imx6_pm_base ccm_base;
227 struct imx6_pm_base gpc_base;
228 struct imx6_pm_base l2_base;
229 u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
230 u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
231 } __aligned(8);
232
imx6_set_int_mem_clk_lpm(bool enable)233 void imx6_set_int_mem_clk_lpm(bool enable)
234 {
235 u32 val = readl_relaxed(ccm_base + CGPR);
236
237 val &= ~BM_CGPR_INT_MEM_CLK_LPM;
238 if (enable)
239 val |= BM_CGPR_INT_MEM_CLK_LPM;
240 writel_relaxed(val, ccm_base + CGPR);
241 }
242
imx6_enable_rbc(bool enable)243 void imx6_enable_rbc(bool enable)
244 {
245 u32 val;
246
247 /*
248 * need to mask all interrupts in GPC before
249 * operating RBC configurations
250 */
251 imx_gpc_mask_all();
252
253 /* configure RBC enable bit */
254 val = readl_relaxed(ccm_base + CCR);
255 val &= ~BM_CCR_RBC_EN;
256 val |= enable ? BM_CCR_RBC_EN : 0;
257 writel_relaxed(val, ccm_base + CCR);
258
259 /* configure RBC count */
260 val = readl_relaxed(ccm_base + CCR);
261 val &= ~BM_CCR_RBC_BYPASS_COUNT;
262 val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
263 writel(val, ccm_base + CCR);
264
265 /*
266 * need to delay at least 2 cycles of CKIL(32K)
267 * due to hardware design requirement, which is
268 * ~61us, here we use 65us for safe
269 */
270 udelay(65);
271
272 /* restore GPC interrupt mask settings */
273 imx_gpc_restore_all();
274 }
275
imx6q_enable_wb(bool enable)276 static void imx6q_enable_wb(bool enable)
277 {
278 u32 val;
279
280 /* configure well bias enable bit */
281 val = readl_relaxed(ccm_base + CLPCR);
282 val &= ~BM_CLPCR_WB_PER_AT_LPM;
283 val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
284 writel_relaxed(val, ccm_base + CLPCR);
285
286 /* configure well bias count */
287 val = readl_relaxed(ccm_base + CCR);
288 val &= ~BM_CCR_WB_COUNT;
289 val |= enable ? BM_CCR_WB_COUNT : 0;
290 writel_relaxed(val, ccm_base + CCR);
291 }
292
imx6_set_lpm(enum mxc_cpu_pwr_mode mode)293 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
294 {
295 u32 val = readl_relaxed(ccm_base + CLPCR);
296
297 val &= ~BM_CLPCR_LPM;
298 switch (mode) {
299 case WAIT_CLOCKED:
300 break;
301 case WAIT_UNCLOCKED:
302 val |= 0x1 << BP_CLPCR_LPM;
303 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
304 break;
305 case STOP_POWER_ON:
306 val |= 0x2 << BP_CLPCR_LPM;
307 val &= ~BM_CLPCR_VSTBY;
308 val &= ~BM_CLPCR_SBYOS;
309 if (cpu_is_imx6sl())
310 val |= BM_CLPCR_BYPASS_PMIC_READY;
311 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
312 cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
313 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
314 else
315 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
316 break;
317 case WAIT_UNCLOCKED_POWER_OFF:
318 val |= 0x1 << BP_CLPCR_LPM;
319 val &= ~BM_CLPCR_VSTBY;
320 val &= ~BM_CLPCR_SBYOS;
321 break;
322 case STOP_POWER_OFF:
323 val |= 0x2 << BP_CLPCR_LPM;
324 val |= 0x3 << BP_CLPCR_STBY_COUNT;
325 val |= BM_CLPCR_VSTBY;
326 val |= BM_CLPCR_SBYOS;
327 if (cpu_is_imx6sl() || cpu_is_imx6sx())
328 val |= BM_CLPCR_BYPASS_PMIC_READY;
329 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
330 cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz())
331 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
332 else
333 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
334 break;
335 default:
336 return -EINVAL;
337 }
338
339 /*
340 * ERR007265: CCM: When improper low-power sequence is used,
341 * the SoC enters low power mode before the ARM core executes WFI.
342 *
343 * Software workaround:
344 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
345 * by setting IOMUX_GPR1_GINT.
346 * 2) Software should then unmask IRQ #32 in GPC before setting CCM
347 * Low-Power mode.
348 * 3) Software should mask IRQ #32 right after CCM Low-Power mode
349 * is set (set bits 0-1 of CCM_CLPCR).
350 *
351 * Note that IRQ #32 is GIC SPI #0.
352 */
353 if (mode != WAIT_CLOCKED)
354 imx_gpc_hwirq_unmask(0);
355 writel_relaxed(val, ccm_base + CLPCR);
356 if (mode != WAIT_CLOCKED)
357 imx_gpc_hwirq_mask(0);
358
359 return 0;
360 }
361
imx6q_suspend_finish(unsigned long val)362 static int imx6q_suspend_finish(unsigned long val)
363 {
364 if (!imx6_suspend_in_ocram_fn) {
365 cpu_do_idle();
366 } else {
367 /*
368 * call low level suspend function in ocram,
369 * as we need to float DDR IO.
370 */
371 local_flush_tlb_all();
372 /* check if need to flush internal L2 cache */
373 if (!((struct imx6_cpu_pm_info *)
374 suspend_ocram_base)->l2_base.vbase)
375 flush_cache_all();
376 imx6_suspend_in_ocram_fn(suspend_ocram_base);
377 }
378
379 return 0;
380 }
381
imx6q_pm_enter(suspend_state_t state)382 static int imx6q_pm_enter(suspend_state_t state)
383 {
384 switch (state) {
385 case PM_SUSPEND_STANDBY:
386 imx6_set_lpm(STOP_POWER_ON);
387 imx6_set_int_mem_clk_lpm(true);
388 imx_gpc_pre_suspend(false);
389 if (cpu_is_imx6sl())
390 imx6sl_set_wait_clk(true);
391 /* Zzz ... */
392 cpu_do_idle();
393 if (cpu_is_imx6sl())
394 imx6sl_set_wait_clk(false);
395 imx_gpc_post_resume();
396 imx6_set_lpm(WAIT_CLOCKED);
397 break;
398 case PM_SUSPEND_MEM:
399 imx6_set_lpm(STOP_POWER_OFF);
400 imx6_set_int_mem_clk_lpm(false);
401 imx6q_enable_wb(true);
402 /*
403 * For suspend into ocram, asm code already take care of
404 * RBC setting, so we do NOT need to do that here.
405 */
406 if (!imx6_suspend_in_ocram_fn)
407 imx6_enable_rbc(true);
408 imx_gpc_pre_suspend(true);
409 imx_anatop_pre_suspend();
410 /* Zzz ... */
411 cpu_suspend(0, imx6q_suspend_finish);
412 if (cpu_is_imx6q() || cpu_is_imx6dl())
413 imx_smp_prepare();
414 imx_anatop_post_resume();
415 imx_gpc_post_resume();
416 imx6_enable_rbc(false);
417 imx6q_enable_wb(false);
418 imx6_set_int_mem_clk_lpm(true);
419 imx6_set_lpm(WAIT_CLOCKED);
420 break;
421 default:
422 return -EINVAL;
423 }
424
425 return 0;
426 }
427
imx6q_pm_valid(suspend_state_t state)428 static int imx6q_pm_valid(suspend_state_t state)
429 {
430 return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
431 }
432
433 static const struct platform_suspend_ops imx6q_pm_ops = {
434 .enter = imx6q_pm_enter,
435 .valid = imx6q_pm_valid,
436 };
437
imx6_pm_get_base(struct imx6_pm_base * base,const char * compat)438 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
439 const char *compat)
440 {
441 struct device_node *node;
442 struct resource res;
443 int ret = 0;
444
445 node = of_find_compatible_node(NULL, NULL, compat);
446 if (!node)
447 return -ENODEV;
448
449 ret = of_address_to_resource(node, 0, &res);
450 if (ret)
451 goto put_node;
452
453 base->pbase = res.start;
454 base->vbase = ioremap(res.start, resource_size(&res));
455 if (!base->vbase)
456 ret = -ENOMEM;
457
458 put_node:
459 of_node_put(node);
460 return ret;
461 }
462
imx6q_suspend_init(const struct imx6_pm_socdata * socdata)463 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
464 {
465 phys_addr_t ocram_pbase;
466 struct device_node *node;
467 struct platform_device *pdev;
468 struct imx6_cpu_pm_info *pm_info;
469 struct gen_pool *ocram_pool;
470 unsigned long ocram_base;
471 int i, ret = 0;
472 const u32 *mmdc_offset_array;
473
474 suspend_set_ops(&imx6q_pm_ops);
475
476 if (!socdata) {
477 pr_warn("%s: invalid argument!\n", __func__);
478 return -EINVAL;
479 }
480
481 node = of_find_compatible_node(NULL, NULL, "mmio-sram");
482 if (!node) {
483 pr_warn("%s: failed to find ocram node!\n", __func__);
484 return -ENODEV;
485 }
486
487 pdev = of_find_device_by_node(node);
488 if (!pdev) {
489 pr_warn("%s: failed to find ocram device!\n", __func__);
490 ret = -ENODEV;
491 goto put_node;
492 }
493
494 ocram_pool = gen_pool_get(&pdev->dev, NULL);
495 if (!ocram_pool) {
496 pr_warn("%s: ocram pool unavailable!\n", __func__);
497 ret = -ENODEV;
498 goto put_device;
499 }
500
501 ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
502 if (!ocram_base) {
503 pr_warn("%s: unable to alloc ocram!\n", __func__);
504 ret = -ENOMEM;
505 goto put_device;
506 }
507
508 ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
509
510 suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
511 MX6Q_SUSPEND_OCRAM_SIZE, false);
512
513 memset(suspend_ocram_base, 0, sizeof(*pm_info));
514 pm_info = suspend_ocram_base;
515 pm_info->pbase = ocram_pbase;
516 pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
517 pm_info->pm_info_size = sizeof(*pm_info);
518
519 /*
520 * ccm physical address is not used by asm code currently,
521 * so get ccm virtual address directly.
522 */
523 pm_info->ccm_base.vbase = ccm_base;
524
525 ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
526 if (ret) {
527 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
528 goto put_device;
529 }
530
531 ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
532 if (ret) {
533 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
534 goto src_map_failed;
535 }
536
537 ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
538 if (ret) {
539 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
540 goto iomuxc_map_failed;
541 }
542
543 ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
544 if (ret) {
545 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
546 goto gpc_map_failed;
547 }
548
549 if (socdata->pl310_compat) {
550 ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
551 if (ret) {
552 pr_warn("%s: failed to get pl310-cache base %d!\n",
553 __func__, ret);
554 goto pl310_cache_map_failed;
555 }
556 }
557
558 pm_info->ddr_type = imx_mmdc_get_ddr_type();
559 pm_info->mmdc_io_num = socdata->mmdc_io_num;
560 mmdc_offset_array = socdata->mmdc_io_offset;
561
562 for (i = 0; i < pm_info->mmdc_io_num; i++) {
563 pm_info->mmdc_io_val[i][0] =
564 mmdc_offset_array[i];
565 pm_info->mmdc_io_val[i][1] =
566 readl_relaxed(pm_info->iomuxc_base.vbase +
567 mmdc_offset_array[i]);
568 }
569
570 imx6_suspend_in_ocram_fn = fncpy(
571 suspend_ocram_base + sizeof(*pm_info),
572 &imx6_suspend,
573 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
574
575 __arm_iomem_set_ro(suspend_ocram_base, MX6Q_SUSPEND_OCRAM_SIZE);
576
577 goto put_device;
578
579 pl310_cache_map_failed:
580 iounmap(pm_info->gpc_base.vbase);
581 gpc_map_failed:
582 iounmap(pm_info->iomuxc_base.vbase);
583 iomuxc_map_failed:
584 iounmap(pm_info->src_base.vbase);
585 src_map_failed:
586 iounmap(pm_info->mmdc_base.vbase);
587 put_device:
588 put_device(&pdev->dev);
589 put_node:
590 of_node_put(node);
591
592 return ret;
593 }
594
imx6_pm_common_init(const struct imx6_pm_socdata * socdata)595 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
596 *socdata)
597 {
598 struct regmap *gpr;
599 int ret;
600
601 WARN_ON(!ccm_base);
602
603 if (IS_ENABLED(CONFIG_SUSPEND)) {
604 ret = imx6q_suspend_init(socdata);
605 if (ret)
606 pr_warn("%s: No DDR LPM support with suspend %d!\n",
607 __func__, ret);
608 }
609
610 /*
611 * This is for SW workaround step #1 of ERR007265, see comments
612 * in imx6_set_lpm for details of this errata.
613 * Force IOMUXC irq pending, so that the interrupt to GPC can be
614 * used to deassert dsm_request signal when the signal gets
615 * asserted unexpectedly.
616 */
617 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
618 if (!IS_ERR(gpr))
619 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
620 IMX6Q_GPR1_GINT);
621 }
622
imx6_pm_stby_poweroff(void)623 static void imx6_pm_stby_poweroff(void)
624 {
625 gic_cpu_if_down(0);
626 imx6_set_lpm(STOP_POWER_OFF);
627 imx6q_suspend_finish(0);
628
629 mdelay(1000);
630
631 pr_emerg("Unable to poweroff system\n");
632 }
633
imx6_pm_stby_poweroff_probe(void)634 static int imx6_pm_stby_poweroff_probe(void)
635 {
636 if (pm_power_off) {
637 pr_warn("%s: pm_power_off already claimed %p %ps!\n",
638 __func__, pm_power_off, pm_power_off);
639 return -EBUSY;
640 }
641
642 pm_power_off = imx6_pm_stby_poweroff;
643 return 0;
644 }
645
imx6_pm_ccm_init(const char * ccm_compat)646 void __init imx6_pm_ccm_init(const char *ccm_compat)
647 {
648 struct device_node *np;
649 u32 val;
650
651 np = of_find_compatible_node(NULL, NULL, ccm_compat);
652 ccm_base = of_iomap(np, 0);
653 BUG_ON(!ccm_base);
654
655 /*
656 * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
657 * clock being shut down unexpectedly by WAIT mode.
658 */
659 val = readl_relaxed(ccm_base + CLPCR);
660 val &= ~BM_CLPCR_LPM;
661 writel_relaxed(val, ccm_base + CLPCR);
662
663 if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
664 imx6_pm_stby_poweroff_probe();
665
666 of_node_put(np);
667 }
668
imx6q_pm_init(void)669 void __init imx6q_pm_init(void)
670 {
671 imx6_pm_common_init(&imx6q_pm_data);
672 }
673
imx6dl_pm_init(void)674 void __init imx6dl_pm_init(void)
675 {
676 imx6_pm_common_init(&imx6dl_pm_data);
677 }
678
imx6sl_pm_init(void)679 void __init imx6sl_pm_init(void)
680 {
681 struct regmap *gpr;
682
683 if (cpu_is_imx6sl()) {
684 imx6_pm_common_init(&imx6sl_pm_data);
685 } else {
686 imx6_pm_common_init(&imx6sll_pm_data);
687 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
688 if (!IS_ERR(gpr))
689 regmap_update_bits(gpr, IOMUXC_GPR5,
690 IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);
691 }
692 }
693
imx6sx_pm_init(void)694 void __init imx6sx_pm_init(void)
695 {
696 imx6_pm_common_init(&imx6sx_pm_data);
697 }
698
imx6ul_pm_init(void)699 void __init imx6ul_pm_init(void)
700 {
701 imx6_pm_common_init(&imx6ul_pm_data);
702 }
703