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/linux/arch/arc/include/asm/
A Dperf_event.h126 static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
127 [C(L1D)] = {
128 [C(OP_READ)] = {
141 [C(L1I)] = {
142 [C(OP_READ)] = {
155 [C(LL)] = {
156 [C(OP_READ)] = {
169 [C(DTLB)] = {
184 [C(ITLB)] = {
198 [C(BPU)] = {
[all …]
/linux/arch/x86/events/zhaoxin/
A Dcore.c51 [C(L1D)] = {
65 [C(L1I)] = {
79 [C(LL)] = {
93 [C(DTLB)] = {
107 [C(ITLB)] = {
121 [C(BPU)] = {
135 [C(NODE)] = {
155 [C(L1D)] = {
169 [C(L1I)] = {
183 [C(LL)] = {
[all …]
/linux/arch/powerpc/perf/
A Dpower10-pmu.c347 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
348 [C(L1D)] = {
362 [C(L1I)] = {
376 [C(LL)] = {
418 [C(BPU)] = {
448 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
449 [C(L1D)] = {
463 [C(L1I)] = {
477 [C(LL)] = {
519 [C(BPU)] = {
[all …]
A Dgeneric-compat-pmu.c175 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
176 [ C(L1D) ] = {
177 [ C(OP_READ) ] = {
190 [ C(L1I) ] = {
191 [ C(OP_READ) ] = {
204 [ C(LL) ] = {
218 [ C(DTLB) ] = {
232 [ C(ITLB) ] = {
246 [ C(BPU) ] = {
260 [ C(NODE) ] = {
[all …]
A Dpower8-pmu.c256 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
257 [ C(L1D) ] = {
258 [ C(OP_READ) ] = {
271 [ C(L1I) ] = {
272 [ C(OP_READ) ] = {
285 [ C(LL) ] = {
299 [ C(DTLB) ] = {
313 [ C(ITLB) ] = {
327 [ C(BPU) ] = {
341 [ C(NODE) ] = {
[all …]
A Dpower9-pmu.c327 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
328 [ C(L1D) ] = {
329 [ C(OP_READ) ] = {
342 [ C(L1I) ] = {
343 [ C(OP_READ) ] = {
356 [ C(LL) ] = {
370 [ C(DTLB) ] = {
384 [ C(ITLB) ] = {
398 [ C(BPU) ] = {
412 [ C(NODE) ] = {
[all …]
A De6500-pmu.c35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
53 [C(LL)] = {
55 [C(OP_READ)] = { 0, 0 },
56 [C(OP_WRITE)] = { 0, 0 },
65 [C(DTLB)] = {
71 [C(BPU)] = {
[all …]
A De500-pmu.c34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
56 [C(OP_READ)] = { 0, 0 },
57 [C(OP_WRITE)] = { 0, 0 },
67 [C(OP_READ)] = { 26, 66 },
68 [C(OP_WRITE)] = { -1, -1 },
[all …]
/linux/arch/sh/kernel/cpu/sh4/
A Dperf_event.c91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
106 [ C(L1I) ] = {
107 [ C(OP_READ) ] = {
121 [ C(LL) ] = {
122 [ C(OP_READ) ] = {
136 [ C(DTLB) ] = {
137 [ C(OP_READ) ] = {
151 [ C(ITLB) ] = {
166 [ C(BPU) ] = {
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
A Dperf_event.c116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
131 [ C(L1I) ] = {
132 [ C(OP_READ) ] = {
146 [ C(LL) ] = {
147 [ C(OP_READ) ] = {
161 [ C(DTLB) ] = {
162 [ C(OP_READ) ] = {
176 [ C(ITLB) ] = {
191 [ C(BPU) ] = {
[all …]
/linux/arch/arm/kernel/
A Dperf_event_v7.c192 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
193 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
195 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
196 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
236 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
239 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
518 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
524 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
526 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
527 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
[all …]
/linux/arch/x86/events/intel/
A Dp6.c28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
33 [ C(OP_WRITE) ] = {
42 [ C(L1I ) ] = {
43 [ C(OP_READ) ] = {
56 [ C(LL ) ] = {
57 [ C(OP_READ) ] = {
70 [ C(DTLB) ] = {
71 [ C(OP_READ) ] = {
84 [ C(ITLB) ] = {
[all …]
A Dcore.c1833 [C(LL)] = {
1895 [C(LL)] = {
1949 [C(LL)] = {
2011 [C(LL)] = {
5821 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
5995 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
5997 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
5999 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
6001 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
6116 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
[all …]
A Dknc.c26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
36 [ C(OP_WRITE) ] = {
45 [ C(L1I ) ] = {
46 [ C(OP_READ) ] = {
59 [ C(LL ) ] = {
60 [ C(OP_READ) ] = {
73 [ C(DTLB) ] = {
74 [ C(OP_READ) ] = {
89 [ C(ITLB) ] = {
[all …]
/linux/lib/
A Dsha1.c60 #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
61 #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
62 #define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) argument
63 #define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D,… argument
64 #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) argument
86 __u32 A, B, C, D, E; in sha1_transform() local
90 C = digest[2]; in sha1_transform()
95 T_0_15( 0, A, B, C, D, E); in sha1_transform()
96 T_0_15( 1, E, A, B, C, D); in sha1_transform()
97 T_0_15( 2, D, E, A, B, C); in sha1_transform()
[all …]
/linux/arch/x86/events/amd/
A Dcore.c26 [ C(L1D) ] = {
40 [ C(L1I ) ] = {
54 [ C(LL ) ] = {
68 [ C(DTLB) ] = {
130 [C(L1D)] = {
144 [C(L1I)] = {
158 [C(LL)] = {
172 [C(DTLB)] = {
186 [C(ITLB)] = {
200 [C(BPU)] = {
[all …]
/linux/arch/sparc/kernel/
A Dperf_event.c221 [C(L1D)] = {
235 [C(L1I)] = {
249 [C(LL)] = {
291 [C(BPU)] = {
359 [C(L1D)] = {
373 [C(L1I)] = {
387 [C(LL)] = {
429 [C(BPU)] = {
494 [C(L1D)] = {
522 [C(LL)] = {
[all …]
/linux/tools/testing/selftests/bpf/progs/
A Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
A Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
A Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/linux/arch/nds32/include/asm/
A Dpmu.h244 [C(L1D)] = {
245 [C(OP_READ)] = {
251 [C(OP_WRITE)] = {
264 [C(L1I)] = {
265 [C(OP_READ)] = {
284 [C(LL)] = {
285 [C(OP_READ)] = {
289 [C(OP_WRITE)] = {
304 [C(DTLB)] = {
322 [C(ITLB)] = {
[all …]
/linux/arch/mips/kernel/
A Dperf_event_mipsxx.c1010 [C(L1D)] = {
1026 [C(L1I)] = {
1043 [C(LL)] = {
1073 [C(BPU)] = {
1091 [C(L1D)] = {
1107 [C(L1I)] = {
1124 [C(LL)] = {
1149 [C(BPU)] = {
1284 [C(LL)] = {
1346 [C(LL)] = {
[all …]
/linux/arch/riscv/kernel/
A Dperf_event.c56 [C(L1D)] = {
57 [C(OP_READ)] = {
70 [C(L1I)] = {
71 [C(OP_READ)] = {
84 [C(LL)] = {
85 [C(OP_READ)] = {
98 [C(DTLB)] = {
99 [C(OP_READ)] = {
112 [C(ITLB)] = {
113 [C(OP_READ)] = {
[all …]
/linux/lib/zstd/common/
A Dcpu.h98 C(sse3, 0)
103 C(vmx, 5)
104 C(smx, 6)
105 C(eist, 7)
106 C(tm2, 8)
109 C(fma, 12)
114 C(dca, 18)
121 C(aes, 25)
124 C(avx, 28)
127 #undef C
[all …]
/linux/arch/arm64/kernel/
A Dperf_event.c60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
75 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
[all …]

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