| /linux/arch/arm/plat-omap/ |
| A D | dma.c | 160 ccr = p->dma_read(CCR, lch); in omap_set_dma_priority()
165 p->dma_write(ccr, CCR, lch); in omap_set_dma_priority()
184 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
262 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
265 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
343 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
346 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
550 p->dma_write(0, CCR, lch); in omap_free_dma()
616 l = p->dma_read(CCR, lch); in omap_start_dma()
629 p->dma_write(l, CCR, lch); in omap_start_dma()
[all …]
|
| /linux/drivers/dma/ |
| A D | txx9dmac.h | 77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
|
| A D | txx9dmac.c | 295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
|
| A D | pl330.c | 340 CCR, enumerator
1264 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1419 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); in _setup_req()
|
| /linux/arch/arm/mach-imx/ |
| A D | pm-imx6.c | 30 #define CCR 0x0 macro
254 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
257 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
260 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
263 writel(val, ccm_base + CCR); in imx6_enable_rbc()
287 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
290 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
|
| /linux/drivers/clocksource/ |
| A D | timer-atmel-tcb.c | 104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
324 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
332 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
348 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
|
| /linux/arch/arm/mach-omap1/ |
| A D | dma.c | 57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
|
| /linux/drivers/pwm/ |
| A D | pwm-atmel-tcb.c | 193 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
198 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
283 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_enable()
551 ATMEL_TC_REG(channel, CCR)); in atmel_tcb_pwm_resume()
|
| /linux/drivers/dma/ti/ |
| A D | omap-dma.c | 457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
495 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
504 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
506 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
517 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
926 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
1538 if (omap_dma_chan_read(c, CCR) & CCR_ENABLE) in omap_dma_busy()
|
| /linux/drivers/counter/ |
| A D | microchip-tcb-capture.c | 133 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_write()
140 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_write()
|
| /linux/arch/arm/mach-omap2/ |
| A D | dma.c | 53 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
|
| /linux/Documentation/translations/zh_CN/parisc/ |
| A D | registers.rst | 28 CR10 (CCR) FPU延迟保存*
|
| /linux/sound/soc/dwc/ |
| A D | local.h | 24 #define CCR 0x010 macro
|
| A D | dwc-i2s.c | 282 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); in dw_i2s_hw_params()
|
| /linux/sound/soc/intel/keembay/ |
| A D | kmb_platform.h | 23 #define CCR 0x010 macro
|
| A D | kmb_platform.c | 656 writel(kmb_i2s->ccr, kmb_i2s->i2s_base + CCR); in kmb_dai_hw_params()
|
| /linux/sound/pci/emu10k1/ |
| A D | emu10k1_callback.c | 422 snd_emu10k1_ptr_write(hw, CCR, ch, 0x1c << 16); in start_voice()
435 snd_emu10k1_ptr_write(hw, CCR, ch, val); in start_voice()
|
| A D | emu10k1_main.c | 66 snd_emu10k1_ptr_write(emu, CCR, ch, 0); in snd_emu10k1_voice_init()
2004 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
|
| /linux/include/linux/ |
| A D | omap-dma.h | 153 CSDP, CCR, CICR, CSR, enumerator
|
| /linux/Documentation/parisc/ |
| A D | registers.rst | 18 CR10 (CCR) lazy FPU saving*
|
| /linux/include/sound/ |
| A D | emu10k1.h | 424 #define CCR 0x09 /* Cache control register */ macro
|
| /linux/Documentation/powerpc/ |
| A D | transactional_memory.rst | 63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
|
| /linux/drivers/tty/ |
| A D | synclink_gt.c | 373 #define CCR 0x89 /* clock control */ macro
3837 wr_reg8(info, CCR, 0x49); in enable_loopback()
4120 wr_reg8(info, CCR, 0x69); in async_mode()
4333 wr_reg8(info, CCR, (unsigned char)val); in sync_mode()
|
| /linux/drivers/video/fbdev/ |
| A D | imsttfb.c | 93 CCR = 0x00000008L,
|